[PATCH V2 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support

Ashish Mhetre
2025-11-25T07:17:23Z

The Command Queue Virtualization (CMDQV) hardware is part of the
SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
virtualizing the command queue for the SMMU.

Add a new device tree binding document for nvidia,tegra264-cmdqv.

Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv
property. This property is a phandle to the CMDQV device node, allowing
the SMMU driver to associate with its corresponding CMDQV instance.
Restrict this property usage to Nvidia Tegra264 only.

Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
---
.../bindings/iommu/arm,smmu-v3.yaml | 30 ++++++++++++-
.../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 42 +++++++++++++++++++
2 files changed, 70 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 75fcf4cb52d9..1c03482e4c61 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -20,7 +20,12 @@ properties:
$nodename:
pattern: "^iommu@[0-9a-f]*"
compatible:
- const: arm,smmu-v3
+ oneOf:
+ - const: arm,smmu-v3
+ - items:
+ - enum:
+ - nvidia,tegra264-smmu
+ - const: arm,smmu-v3

reg:
maxItems: 1
@@ -58,6 +63,15 @@ properties:

msi-parent: true

+ nvidia,cmdqv:
+ description: |
+ A phandle to its pairing CMDQV extension for an implementation on NVIDIA
+ Tegra SoC.
+
+ If this property is absent, CMDQ-Virtualization won't be used and SMMU
+ will only use its own CMDQ.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
hisilicon,broken-prefetch-cmd:
type: boolean
description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
@@ -69,6 +83,17 @@ properties:
register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
doesn't support SMMU page1 register space.

+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: nvidia,tegra264-smmu
+ then:
+ properties:
+ nvidia,cmdqv: false
+
required:
- compatible
- reg
@@ -82,7 +107,7 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>

iommu@2b400000 {
- compatible = "arm,smmu-v3";
+ compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
reg = <0x2b400000 0x20000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
@@ -92,4 +117,5 @@ examples:
dma-coherent;
#iommu-cells = <1>;
msi-parent = <&its 0xff0000>;
+ nvidia,cmdqv = <&cmdqv>;
};
diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
new file mode 100644
index 000000000000..3f5006a59805
--- /dev/null
+++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/nvidia,tegra264-cmdqv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra264 CMDQV
+
+description:
+ The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation
+ on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU.
+
+maintainers:
+ - Nicolin Chen <nicolinc@nvidia.com>
+
+properties:
+ compatible:
+ const: nvidia,tegra264-cmdqv
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ cmdqv@5200000 {
+ compatible = "nvidia,tegra264-cmdqv";
+ reg = <0x5200000 0x830000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ };
--
2.25.1