From: Hal Feng <hal.feng@starfivetech.com>
To: Emil Renner Berthing <emil.renner.berthing@canonical.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: Conor Dooley <conor@kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Ben Dooks <ben.dooks@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
"Marc Zyngier" <maz@kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
Date: Sat, 25 Mar 2023 22:26:19 +0800 [thread overview]
Message-ID: <cfcbbe7f-9d9a-dcd8-5757-1c4e8b06104b@starfivetech.com> (raw)
In-Reply-To: <CAJM55Z-dKKpBJAof1cuAombBFckEhvZ00o6MZHT_KN+baKRc0g@mail.gmail.com>
On Fri, 24 Mar 2023 10:39:36 +0100, Emil Renner Berthing wrote:
> On Thu, 23 Mar 2023 at 10:02, Conor Dooley <conor.dooley@microchip.com> wrote:
>>
>> Hal, Emil,
>>
>> On Thu, Mar 23, 2023 at 03:44:41PM +0800, Hal Feng wrote:
>> > On Wed, 22 Mar 2023 21:53:37 +0000, Conor Dooley wrote:
>> > > On Mon, Mar 20, 2023 at 06:37:40PM +0800, Hal Feng wrote:
>> > >> From: Emil Renner Berthing <kernel@esmil.dk>
>> > >>
>> > >> Add bindings for the system clock and reset generator (SYSCRG) on the
>> > >> JH7110 RISC-V SoC by StarFive Ltd.
>> > >>
>> > >> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> > >> Reviewed-by: Rob Herring <robh@kernel.org>
>> > >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> > >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> > >> ---
>> > >> .../clock/starfive,jh7110-syscrg.yaml | 104 +++++++++
>> > >> MAINTAINERS | 8 +-
>> > >> .../dt-bindings/clock/starfive,jh7110-crg.h | 203 ++++++++++++++++++
>> > >> .../dt-bindings/reset/starfive,jh7110-crg.h | 142 ++++++++++++
>> > >> 4 files changed, 454 insertions(+), 3 deletions(-)
>> > >> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> > >> create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
>> > >> create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
>> > >>
>> > >> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> > >> new file mode 100644
>> > >> index 000000000000..84373ae31644
>> > >> --- /dev/null
>> > >> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> > >> @@ -0,0 +1,104 @@
>> > >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> > >> +%YAML 1.2
>> > >> +---
>> > >> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
>> > >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> > >> +
>> > >> +title: StarFive JH7110 System Clock and Reset Generator
>> > >> +
>> > >> +maintainers:
>> > >> + - Emil Renner Berthing <kernel@esmil.dk>
>> > >> +
>> > >> +properties:
>> > >> + compatible:
>> > >> + const: starfive,jh7110-syscrg
>> > >> +
>> > >> + reg:
>> > >> + maxItems: 1
>> > >> +
>> > >> + clocks:
>> > >> + oneOf:
>> > >> + - items:
>> > >> + - description: Main Oscillator (24 MHz)
>> > >> + - description: GMAC1 RMII reference or GMAC1 RGMII RX
>> > >> + - description: External I2S TX bit clock
>> > >> + - description: External I2S TX left/right channel clock
>> > >> + - description: External I2S RX bit clock
>> > >> + - description: External I2S RX left/right channel clock
>> > >> + - description: External TDM clock
>> > >> + - description: External audio master clock
>> > >> +
>> > >> + - items:
>> > >> + - description: Main Oscillator (24 MHz)
>> > >> + - description: GMAC1 RMII reference
>> > >> + - description: GMAC1 RGMII RX
>> > >> + - description: External I2S TX bit clock
>> > >> + - description: External I2S TX left/right channel clock
>> > >> + - description: External I2S RX bit clock
>> > >> + - description: External I2S RX left/right channel clock
>> > >> + - description: External TDM clock
>> > >> + - description: External audio master clock
>> > >> +
>> > >> + clock-names:
>> > >> + oneOf:
>> > >> + - items:
>> > >> + - const: osc
>> > >> + - enum:
>> > >> + - gmac1_rmii_refin
>> > >> + - gmac1_rgmii_rxin
>> > >> + - const: i2stx_bclk_ext
>> > >> + - const: i2stx_lrck_ext
>> > >> + - const: i2srx_bclk_ext
>> > >> + - const: i2srx_lrck_ext
>> > >> + - const: tdm_ext
>> > >> + - const: mclk_ext
>> > >> +
>> > >> + - items:
>> > >> + - const: osc
>> > >> + - const: gmac1_rmii_refin
>> > >> + - const: gmac1_rgmii_rxin
>> > >> + - const: i2stx_bclk_ext
>> > >> + - const: i2stx_lrck_ext
>> > >> + - const: i2srx_bclk_ext
>> > >> + - const: i2srx_lrck_ext
>> > >> + - const: tdm_ext
>> > >> + - const: mclk_ext
>> > >
>> > > I'm sorry to be a bit of a bore about these bindings, but Emil mentioned
>> > > to me today that he had some doubts about whether any of these audio
>> > > clocks are actually required.
>> > > I've had a bit of a look at the driver, cos the TRM that I have doesn't
>> > > describe the clock tree (from what recall at least) and I think he is
>> > > right.
>> > > For example, the TDM clock:
>> > > + JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
>> > > + JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
>> > > + JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
>> > > + JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
>> > > + JH7110_SYSCLK_TDM_INTERNAL,
>> > > + JH7110_SYSCLK_TDM_EXT),
>> > >
>> > > Hopefully, I'm not making a balls of something here, but it looks like I
>> > > can choose an internal TDM clock, that is based on JH7110_SYSCLK_MCLK,
>> > > which in turn comes from either an internal or external source.
>> > > If I am following correctly, that'd be:
>> > > + JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
>> > >
>> > > Which in turn comes from:
>> > > + JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
>> > >
>> > > This leaves me wondering which clocks are *actually* required for a
>> > > functioning system - is it actually just osc and one of gmac1_rmii_refin
>> > > or gmac1_rgmii_rxin.
>> >
>> > As I had mentioned somewhere before, some audio clocks need to change their
>> > parents at different stages of work. I should explain in detail here.
>> >
>> > For the i2s*_ext clocks, we should use these external clocks as parents when
>> > the I2S module is working in the slave mode, while we should use the internal
>> > clocks as parents when the I2S module is working in the master mode.
>
> Right, so what Hal is saying here is that the i2s*_ext clocks are only
> needed if the board is designed to have i2s modules in slave mode.
I don't think we want to describe the dt-bindings of clock controllers according
to the board design.
As I said in v5, IMO, the "optional" here means whether the clock is optional
in the sense that we are able to run all designed functions on the SoC.
>
>> > For the tdm_ext clock, we use it as the clock source for an accurate playback
>> > rate. If we use the internal clock as clock source, the TDM can't work
>> > normally, because it can't get a required rate from the internal divider.
>> > By the way, note that we need to use the internal clock as clock source when
>> > we try to reset the tdm clock, otherwise, the reset will fail.
>> >
>> > For the mclk_ext clock, which is 12.288MHz, it's used as the clock source
>> > through all the running time, otherwise, the daughter clocks can't get the
>> > required rate from the internal PLL2 clock (1188MHz) through dividers.
>
> Right, so PLL2 is 1188MHz on the VisionFive 2.
>
> Hal: But is it not possible to program the PLL2 to run at a multiple
> of 12.288MHz in some other configuration?
Yeah, we can definitely set the PLL2 at a multiple of 12.288MHz as what we did in
the v1. We changed it to 1188MHz for supporting dual-screen display.
Best regards,
Hal
>
>> > So all these audio external clocks (i2s*_ext / tdm_ext / mclk_ext) are
>> > actually required.
>>
>> Okay. I think I am okay with leaving the binding as-is then, and if
>> someone needs to omit the entire audio subsystem on the SoC, they can
>> follow Stephen's suggestion.
>>
>> @Emil, is that okay with you?
>
> Conor: I'm fine with the bindings like this. I just want to make sure
> that we all have the same idea of what is "optional" and should be
> marked as such in the bindings.
>
> /Emil
next prev parent reply other threads:[~2023-03-25 14:26 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 10:37 [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-03-20 10:37 ` [PATCH v6 01/21] clk: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 02/21] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-03-20 10:37 ` [PATCH v6 03/21] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-03-20 10:37 ` [PATCH v6 04/21] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 05/21] reset: starfive: Replace SOC_STARFIVE with ARCH_STARFIVE Hal Feng
2023-03-20 10:37 ` [PATCH v6 06/21] reset: Create subdirectory for StarFive drivers Hal Feng
2023-03-20 10:37 ` [PATCH v6 07/21] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-03-20 10:37 ` [PATCH v6 08/21] reset: starfive: Extract the " Hal Feng
2023-03-20 10:37 ` [PATCH v6 09/21] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-03-20 10:37 ` [PATCH v6 10/21] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-03-20 10:37 ` [PATCH v6 11/21] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-03-22 21:53 ` Conor Dooley
2023-03-22 23:57 ` Stephen Boyd
2023-03-23 7:44 ` Hal Feng
2023-03-23 9:01 ` Conor Dooley
2023-03-24 9:39 ` Emil Renner Berthing
2023-03-25 14:26 ` Hal Feng [this message]
2023-03-20 10:37 ` [PATCH v6 12/21] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` [PATCH v6 13/21] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-03-24 14:39 ` Emil Renner Berthing
2023-03-25 15:54 ` Hal Feng
2023-03-26 20:06 ` Emil Renner Berthing
2023-03-26 20:13 ` Emil Renner Berthing
2023-03-27 18:51 ` Stephen Boyd
2023-03-27 23:08 ` Emil Renner Berthing
2023-03-20 10:37 ` [PATCH v6 14/21] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-03-20 10:37 ` [PATCH v6 15/21] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-03-20 10:37 ` [PATCH v6 16/21] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-03-20 10:37 ` [PATCH v6 17/21] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-03-20 10:37 ` [PATCH v6 18/21] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-03-20 10:37 ` [PATCH v6 19/21] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-03-22 22:02 ` Conor Dooley
2023-03-23 9:03 ` Conor Dooley
2023-03-24 7:03 ` Hal Feng
2023-03-20 10:37 ` [PATCH v6 20/21] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-03-20 10:37 ` [PATCH v6 21/21] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-03-21 23:03 ` [PATCH v6 00/21] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Conor Dooley
2023-03-21 23:57 ` Stephen Boyd
2023-03-22 21:06 ` Conor Dooley
2023-03-22 23:53 ` Stephen Boyd
2023-03-27 22:50 ` Conor Dooley
2023-03-28 1:42 ` Hal Feng
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