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From: Alexander Sverdlin <alexander.sverdlin@gmail.com>
To: Anshumali Gaur <agaur@marvell.com>,
	conor.dooley@microchip.com,  ulf.hansson@linaro.org,
	arnd@arndb.de, linus.walleij@linaro.org,
	 nikita.shubin@maquefel.me, vkoul@kernel.org, cyy@cyyself.name,
	 krzysztof.kozlowski@linaro.org, linux-kernel@vger.kernel.org,
	 sgoutham@marvell.com
Subject: Re: [PATCH 1/4] soc: marvell: Add a general purpose RVU PF driver
Date: Sat, 21 Sep 2024 23:38:32 +0200	[thread overview]
Message-ID: <cff2b9b064c22e185bad42010ded7e1559fe672f.camel@gmail.com> (raw)
In-Reply-To: <20240920112318.2722488-2-agaur@marvell.com>

Hi Anshumali!

On Fri, 2024-09-20 at 16:53 +0530, Anshumali Gaur wrote:
> Resource virtualization unit (RVU) on Marvell's Octeon series of
> silicons maps HW resources from the network, crypto and other
> functional blocks into PCI-compatible physical and virtual functions.
> Each functional block again has multiple local functions (LFs) for
> provisioning to PCI devices.
> RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual
> functions (VFs). And RVU admin function (AF) is the one which manages
> all the resources (local functions etc) in the system.
> 
> Functionality of these PFs and VFs depends on which block LFs are
> attached to them. Depending on usecase some PFs might support IO
> (ie LFs attached) and some may not. For the usecases where PF
> doesn't (need to) support IO, PF's driver will be limited to below
> functionality.
> 1. Creating and destroying of PCIe SRIOV VFs
> 2. Support mailbox communication between VFs and admin function
>    (RVU AF)
> 3. PCIe Function level reset (FLR) for VFs
> 
> For such PFs this patch series adds a general purpose driver which
> supports above functionality. This will avoid duplicating same
> functionality for different RVU PFs.
> 
> This patch adds basic stub PF driver with PCI device init logic and
> SRIOV enable/disable support.
> 
> Signed-off-by: Anshumali Gaur <agaur@marvell.com>
> ---
> 

[]

> diff --git a/drivers/soc/marvell/rvu_gen_pf/gen_pf.h b/drivers/soc/marvell/rvu_gen_pf/gen_pf.h
> new file mode 100644
> index 000000000000..4cf12e65a526
> --- /dev/null
> +++ b/drivers/soc/marvell/rvu_gen_pf/gen_pf.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Marvell Octeon RVU Generic Physical Function driver
> + *
> + * Copyright (C) 2024 Marvell.
> + */
> +#include <linux/device.h>
> +#include <linux/pci.h>
> +
> +#define RVU_PFFUNC(pf, func)    \
> +	((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) | \
> +	(((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT))
> +
> +struct gen_pf_dev {
> +	struct pci_dev          *pdev;
> +	struct device           *dev;
> +	void __iomem		*reg_base;
> +	int                     pf;
> +	u8                      total_vfs;
> +};

The above struct has strange indentation with tabs and spaces.

-- 
Alexander Sverdlin.


  parent reply	other threads:[~2024-09-21 21:38 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-20 11:23 [PATCH 0/4] soc: marvell: Add a general purpose RVU physical Anshumali Gaur
2024-09-20 11:23 ` [PATCH 1/4] soc: marvell: Add a general purpose RVU PF driver Anshumali Gaur
2024-09-20 22:30   ` Alexander Sverdlin
2024-09-21 21:38   ` Alexander Sverdlin [this message]
2024-09-20 11:23 ` [PATCH 2/4] soc: marvell: rvu-pf: Add PF to AF mailbox communication support Anshumali Gaur
2024-09-21 21:43   ` Alexander Sverdlin
2024-09-24 23:09   ` Alexander Sverdlin
2024-09-20 11:23 ` [PATCH 3/4] soc: marvell: rvu-pf: Add mailbox communication btw RVU VFs and PF Anshumali Gaur
2024-09-21 22:22   ` Alexander Sverdlin
2024-09-20 11:23 ` [PATCH 4/4] soc: marvell: rvu-pf: Handle function level reset (FLR) IRQs for VFs Anshumali Gaur
2024-09-21 22:49   ` Alexander Sverdlin
2024-09-25  9:13     ` Anshumali Gaur
2024-09-25  9:19       ` Alexander Sverdlin
2024-09-25 12:46         ` Anshumali Gaur

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