RE: [PATCH v2 2/5] clk: Add support for fundamental zynq clks

Michal Simek
2012-11-14T15:13:06Z

> -----Original Message-----
> From: Josh Cartwright [mailto:josh.cartwright@ni.com]
> Sent: Tuesday, November 13, 2012 11:03 PM
> To: Soren Brinkmann; Michal Simek
> Cc: Mike Turquette; Rob Herring; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; John Linn; arm@kernel.org
> Subject: Re: [PATCH v2 2/5] clk: Add support for fundamental zynq clks
>
> On Thu, Nov 08, 2012 at 03:28:07PM -0800, Soren Brinkmann wrote:
> > One note below:
> >
> > On Wed, Oct 31, 2012 at 12:58:52PM -0600, Josh Cartwright wrote:
> [..]
> > > --- /dev/null
> > > +++ b/drivers/clk/clk-zynq.c
> [..]
> > > +struct zynq_periph_clk {
> > > + struct clk_hw hw;
> > > + struct clk_onecell_data onecell_data;
> > > + struct clk *gates[2];
> > > + void __iomem *clk_ctrl;
> > > + spinlock_t clkact_lock;
> > > +};
> > > +
> > > +#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk,
> hw)
> > > +
> > > +static const u8 periph_clk_parent_map[] = {
> > > + 0, 0, 1, 2
> > > +};
> > > +#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 3) >> 4])
> >
> > I think this should be:
> > #define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >>
> 4])
>
> Yes indeed it should be, thanks.
>
> Michal- I'll just be following up with a v3 of this patch instead of spinning up the
> whole set to save myself some time. If you'd rather I spin up the whole set, let
> me know.

No problem with that.

thanks,
Michal

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