[PATCH v3 -tip x86/apic 0/2] PCI/MSI: Allocate as many multiple-MSIs as requested

[Alexander Gordeev <agordeev@redhat.com>]

This series is against tip's x86/apic branch.

Allow conserving interrupt resources when PCI devices in multiple-MSI
mode send a number of MSIs which is not a power-of-two. This update
will prevent wasting of any resources associated with unused MSIs in
general (i.e. IRQ descriptors) and x86 interrupt vectors in particular
(the latter are notoriously scarce).

Recently PLX Technology confirmed they do have a relevant hardware,
i.e. their new PEX8796 chip can send 18 MSIs.


Changes from v2:
	- patch 2/2 changelog message elaborated

Changes from v1:
	- do not conserve on IRTEs to prevent possible security
	  hole when one device accesses other device's IRTEs


Patch 1 is a change to the generic MSI code
Patch 2 is the x86 enablement

Alexander Gordeev (2):
  PCI/MSI: Allocate as many multiple-MSIs as requested
  x86/MSI: Conserve interrupt resources when using multiple-MSIs

 drivers/iommu/irq_remapping.c |   12 +++++++-----
 drivers/pci/msi.c             |   10 ++++++++--
 include/linux/msi.h           |    1 +
 3 files changed, 16 insertions(+), 7 deletions(-)

-- 
1.7.7.6


-- 
Regards,
Alexander Gordeev
agordeev@redhat.com