From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753481AbcANM4P (ORCPT ); Thu, 14 Jan 2016 07:56:15 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:36614 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753099AbcANM4N (ORCPT ); Thu, 14 Jan 2016 07:56:13 -0500 From: Jan Glauber X-Google-Original-From: Jan Glauber To: Will Deacon , Mark Rutland Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jan Glauber Subject: [RFC PATCH 0/5] Cavium ThunderX PMU support Date: Thu, 14 Jan 2016 13:55:40 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Will & Mark, please have a look at these patches for perf PMU support. The Cavium PMU stuff should be pretty generic but the long cycle counter bit will change all ARMv8 PMUs and needs careful review. Thanks, Jan Jan Glauber (5): arm64/perf: Rename Cortex A57 events arm64/perf: Add Cavium ThunderX PMU support arm64: dts: Add Cavium ThunderX specific PMU arm64/perf: Enable PMCR long cycle counter bit arm64/perf: Extend event mask for ARMv8.1 Documentation/devicetree/bindings/arm/pmu.txt | 1 + arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 5 + arch/arm64/kernel/perf_event.c | 145 ++++++++++++++++++++------ drivers/perf/arm_pmu.c | 5 +- include/linux/perf/arm_pmu.h | 4 +- 5 files changed, 125 insertions(+), 35 deletions(-) -- 1.9.1