From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1946957AbcBRQug (ORCPT ); Thu, 18 Feb 2016 11:50:36 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:36415 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1946815AbcBRQuf (ORCPT ); Thu, 18 Feb 2016 11:50:35 -0500 From: Jan Glauber To: Will Deacon , Mark Rutland Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jan Glauber Subject: [PATCH v4 0/5] Cavium ThunderX PMU support Date: Thu, 18 Feb 2016 17:50:09 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, this should address all comments. With the simplified event mask arm isn't touched anymore and also the cpuid check vanished. Changes to v3: - renamed A57 events to IMPDEF - changed comment about 64 bit cycle counter overflow - unconditionally increase event mask Changes to v2: - fixed arm compile errors Changes to v1: - renamed thunderx dt pmu binding to thunder Jan -------------------------------------------------------- Jan Glauber (5): arm64/perf: Rename Cortex A57 events arm64/perf: Add Cavium ThunderX PMU support arm64: dts: Add Cavium ThunderX specific PMU arm64/perf: Enable PMCR long cycle counter bit arm64/perf: Extend event mask for ARMv8.1 Documentation/devicetree/bindings/arm/pmu.txt | 1 + arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 5 ++ arch/arm64/kernel/perf_event.c | 120 +++++++++++++++++++++----- 3 files changed, 105 insertions(+), 21 deletions(-) -- 1.9.1