[PATCH v2 2/3] perf/x86/amd/uncore: Update number of uncore counters

Janakarajan Natarajan
2017-01-16T23:37:03Z

This patch updates the AMD uncore driver to support AMD Family17h
processors. In Family17h, there are two extra last level cache counters.

The maximum available counters is increased and the number of counters
for each uncore type is now based on the family.

Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com>
---
arch/x86/events/amd/uncore.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 24c8537..20af57f 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -22,13 +22,17 @@

#define NUM_COUNTERS_NB 4
#define NUM_COUNTERS_L2 4
-#define MAX_COUNTERS NUM_COUNTERS_NB
+#define NUM_COUNTERS_L3 6
+#define MAX_COUNTERS 6

#define RDPMC_BASE_NB 6
#define RDPMC_BASE_LLC 10

#define COUNTER_SHIFT 16

+static int num_counters_llc;
+static int num_counters_nb;
+
static HLIST_HEAD(uncore_unused_list);

struct amd_uncore {
@@ -303,7 +307,7 @@ static int amd_uncore_cpu_up_prepare(unsigned int cpu)
if (!uncore_nb)
goto fail;
uncore_nb->cpu = cpu;
- uncore_nb->num_counters = NUM_COUNTERS_NB;
+ uncore_nb->num_counters = num_counters_nb;
uncore_nb->rdpmc_base = RDPMC_BASE_NB;
uncore_nb->msr_base = MSR_F15H_NB_PERF_CTL;
uncore_nb->active_mask = &amd_nb_active_mask;
@@ -317,7 +321,7 @@ static int amd_uncore_cpu_up_prepare(unsigned int cpu)
if (!uncore_llc)
goto fail;
uncore_llc->cpu = cpu;
- uncore_llc->num_counters = NUM_COUNTERS_L2;
+ uncore_llc->num_counters = num_counters_llc;
uncore_llc->rdpmc_base = RDPMC_BASE_LLC;
uncore_llc->msr_base = MSR_F16H_L2I_PERF_CTL;
uncore_llc->active_mask = &amd_llc_active_mask;
@@ -492,6 +496,27 @@ static int __init amd_uncore_init(void)
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
goto fail_nodev;

+ switch(boot_cpu_data.x86) {
+ case 23:
+ /* Family 17h */
+ num_counters_nb = NUM_COUNTERS_NB;
+ num_counters_llc = NUM_COUNTERS_L3;
+ break;
+ case 22:
+ /* Family 16h. May change */
+ num_counters_nb = NUM_COUNTERS_NB;
+ num_counters_llc = NUM_COUNTERS_L2;
+ break;
+ default:
+ /*
+ * All prior families have the same number of
+ * NorthBridge and Last level cache counters
+ */
+ num_counters_nb = NUM_COUNTERS_NB;
+ num_counters_llc = NUM_COUNTERS_L2;
+ break;
+ }