* [PATCH 01/13] openrisc: use shadow registers to save regs on exception
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
@ 2017-08-30 21:58 ` Stafford Horne
2017-09-01 8:02 ` [OpenRISC] " Geert Uytterhoeven
2017-08-30 21:58 ` [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne
` (11 subsequent siblings)
12 siblings, 1 reply; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 21:58 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stefan Kristiansson, Stafford Horne, Jonas Bonn,
Masahiro Yamada, Andrew Morton
From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Previously, the area between 0x0-0x100 have been used as a
"scratch" memory area to temporarily store regs during
exception entry.
In a multi-core environment, this will not work.
This change is to use shadow registers for nested context.
Currently only the "critical" temp load/stores are covered,
the EMERGENCY_PRINT ones are left as is (when they are used,
it's game over anyway), they need to be handled as well in the
future.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 10 +++++
arch/openrisc/kernel/head.S | 95 ++++++++++++++++++++++++++++++++-------------
2 files changed, 79 insertions(+), 26 deletions(-)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 1e95920b0737..ba8ae92ec5fb 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -121,6 +121,16 @@ config OPENRISC_NO_SPR_SR_DSX
Say N here if you know that your OpenRISC processor has
SPR_SR_DSX bit implemented. Say Y if you are unsure.
+config OPENRISC_HAVE_SHADOW_GPRS
+ bool "Support for shadow gpr files"
+ help
+ Say Y here if your OpenRISC processor features shadowed
+ register files. They will in such case be used as a
+ scratch reg storage on exception entry.
+
+ On SMP systems, this feature is mandatory.
+ On a unicore system it's safe to say N here if you are unsure.
+
config CMDLINE
string "Default kernel command string"
default ""
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1e87913576e3..1e49895408f4 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -49,9 +49,31 @@
/* ============================================[ tmp store locations ]=== */
+#define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32)
+
/*
* emergency_print temporary stores
*/
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
+#define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
+
+#define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
+#define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
+
+#define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
+#define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
+
+#define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
+#define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
+
+#define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
+#define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
+
+#define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
+#define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
#define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
#define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
@@ -70,13 +92,28 @@
#define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
#define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
+#endif
/*
* TLB miss handlers temorary stores
*/
-#define EXCEPTION_STORE_GPR9 l.sw 0x10(r0),r9
-#define EXCEPTION_LOAD_GPR9 l.lwz r9,0x10(r0)
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
+#define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
+
+#define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
+#define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
+#define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
+#define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
+
+#define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
+#define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
+
+#define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
+#define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
#define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
#define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
@@ -92,26 +129,32 @@
#define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
#define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
+#endif
/*
* EXCEPTION_HANDLE temporary stores
*/
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
+#define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
+
+#define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
+#define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
+
+#define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
+#define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
#define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
#define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
#define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
#define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
-#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
+#define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
#define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
-
-/*
- * For UNHANLDED_EXCEPTION
- */
-
-#define EXCEPTION_T_STORE_GPR31 l.sw 0x84(r0),r31
-#define EXCEPTION_T_LOAD_GPR31(reg) l.lwz reg,0x84(r0)
+#endif
/* =========================================================[ macros ]=== */
@@ -226,7 +269,7 @@
*
*/
#define UNHANDLED_EXCEPTION(handler) \
- EXCEPTION_T_STORE_GPR31 ;\
+ EXCEPTION_T_STORE_GPR30 ;\
EXCEPTION_T_STORE_GPR10 ;\
EXCEPTION_T_STORE_SP ;\
/* temporary store r3, r9 into r1, r10 */ ;\
@@ -255,35 +298,35 @@
/* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
/* r12: temp, syscall indicator, r13 temp */ ;\
l.addi r1,r1,-(INT_FRAME_SIZE) ;\
- /* r1 is KSP, r31 is __pa(KSP) */ ;\
- tophys (r31,r1) ;\
- l.sw PT_GPR12(r31),r12 ;\
+ /* r1 is KSP, r30 is __pa(KSP) */ ;\
+ tophys (r30,r1) ;\
+ l.sw PT_GPR12(r30),r12 ;\
l.mfspr r12,r0,SPR_EPCR_BASE ;\
- l.sw PT_PC(r31),r12 ;\
+ l.sw PT_PC(r30),r12 ;\
l.mfspr r12,r0,SPR_ESR_BASE ;\
- l.sw PT_SR(r31),r12 ;\
+ l.sw PT_SR(r30),r12 ;\
/* save r31 */ ;\
- EXCEPTION_T_LOAD_GPR31(r12) ;\
- l.sw PT_GPR31(r31),r12 ;\
+ EXCEPTION_T_LOAD_GPR30(r12) ;\
+ l.sw PT_GPR30(r30),r12 ;\
/* save r10 as was prior to exception */ ;\
EXCEPTION_T_LOAD_GPR10(r12) ;\
- l.sw PT_GPR10(r31),r12 ;\
+ l.sw PT_GPR10(r30),r12 ;\
/* save PT_SP as was prior to exception */ ;\
EXCEPTION_T_LOAD_SP(r12) ;\
- l.sw PT_SP(r31),r12 ;\
- l.sw PT_GPR13(r31),r13 ;\
+ l.sw PT_SP(r30),r12 ;\
+ l.sw PT_GPR13(r30),r13 ;\
/* --> */ ;\
/* save exception r4, set r4 = EA */ ;\
- l.sw PT_GPR4(r31),r4 ;\
+ l.sw PT_GPR4(r30),r4 ;\
l.mfspr r4,r0,SPR_EEAR_BASE ;\
/* r12 == 1 if we come from syscall */ ;\
CLEAR_GPR(r12) ;\
/* ----- play a MMU trick ----- */ ;\
- l.ori r31,r0,(EXCEPTION_SR) ;\
- l.mtspr r0,r31,SPR_ESR_BASE ;\
+ l.ori r30,r0,(EXCEPTION_SR) ;\
+ l.mtspr r0,r30,SPR_ESR_BASE ;\
/* r31: EA address of handler */ ;\
- LOAD_SYMBOL_2_GPR(r31,handler) ;\
- l.mtspr r0,r31,SPR_EPCR_BASE ;\
+ LOAD_SYMBOL_2_GPR(r30,handler) ;\
+ l.mtspr r0,r30,SPR_EPCR_BASE ;\
l.rfe
/* =====================================================[ exceptions] === */
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save regs on exception
2017-08-30 21:58 ` [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
@ 2017-09-01 8:02 ` Geert Uytterhoeven
2017-09-01 8:03 ` Geert Uytterhoeven
0 siblings, 1 reply; 34+ messages in thread
From: Geert Uytterhoeven @ 2017-09-01 8:02 UTC (permalink / raw)
To: Stafford Horne; +Cc: LKML, Jonas Bonn, Masahiro Yamada, Openrisc, Andrew Morton
On Wed, Aug 30, 2017 at 11:58 PM, Stafford Horne <shorne@gmail.com> wrote:
> --- a/arch/openrisc/Kconfig
> +++ b/arch/openrisc/Kconfig
> @@ -121,6 +121,16 @@ config OPENRISC_NO_SPR_SR_DSX
> Say N here if you know that your OpenRISC processor has
> SPR_SR_DSX bit implemented. Say Y if you are unsure.
>
> +config OPENRISC_HAVE_SHADOW_GPRS
> + bool "Support for shadow gpr files"
default y if SMP?
> + help
> + Say Y here if your OpenRISC processor features shadowed
> + register files. They will in such case be used as a
> + scratch reg storage on exception entry.
> +
> + On SMP systems, this feature is mandatory.
> + On a unicore system it's safe to say N here if you are unsure.
> +
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save regs on exception
2017-09-01 8:02 ` [OpenRISC] " Geert Uytterhoeven
@ 2017-09-01 8:03 ` Geert Uytterhoeven
2017-09-01 8:26 ` Stafford Horne
0 siblings, 1 reply; 34+ messages in thread
From: Geert Uytterhoeven @ 2017-09-01 8:03 UTC (permalink / raw)
To: Stafford Horne; +Cc: LKML, Jonas Bonn, Masahiro Yamada, Openrisc, Andrew Morton
On Fri, Sep 1, 2017 at 10:02 AM, Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Wed, Aug 30, 2017 at 11:58 PM, Stafford Horne <shorne@gmail.com> wrote:
>> --- a/arch/openrisc/Kconfig
>> +++ b/arch/openrisc/Kconfig
>> @@ -121,6 +121,16 @@ config OPENRISC_NO_SPR_SR_DSX
>> Say N here if you know that your OpenRISC processor has
>> SPR_SR_DSX bit implemented. Say Y if you are unsure.
>>
>> +config OPENRISC_HAVE_SHADOW_GPRS
>> + bool "Support for shadow gpr files"
>
> default y if SMP?
Oops, that's not sufficient.
bool "Support for shadow gpr files" if !SMP
default y if SMP
>> + help
>> + Say Y here if your OpenRISC processor features shadowed
>> + register files. They will in such case be used as a
>> + scratch reg storage on exception entry.
>> +
>> + On SMP systems, this feature is mandatory.
>> + On a unicore system it's safe to say N here if you are unsure.
>> +
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [OpenRISC] [PATCH 01/13] openrisc: use shadow registers to save regs on exception
2017-09-01 8:03 ` Geert Uytterhoeven
@ 2017-09-01 8:26 ` Stafford Horne
0 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-09-01 8:26 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: LKML, Jonas Bonn, Masahiro Yamada, Openrisc, Andrew Morton
On Fri, Sep 01, 2017 at 10:03:44AM +0200, Geert Uytterhoeven wrote:
> On Fri, Sep 1, 2017 at 10:02 AM, Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Wed, Aug 30, 2017 at 11:58 PM, Stafford Horne <shorne@gmail.com> wrote:
> >> --- a/arch/openrisc/Kconfig
> >> +++ b/arch/openrisc/Kconfig
> >> @@ -121,6 +121,16 @@ config OPENRISC_NO_SPR_SR_DSX
> >> Say N here if you know that your OpenRISC processor has
> >> SPR_SR_DSX bit implemented. Say Y if you are unsure.
> >>
> >> +config OPENRISC_HAVE_SHADOW_GPRS
> >> + bool "Support for shadow gpr files"
> >
> > default y if SMP?
>
> Oops, that's not sufficient.
>
> bool "Support for shadow gpr files" if !SMP
> default y if SMP
Thanks yes, the help text says its mandatory. That should be forced as you
showed.
-Stafford
> >> + help
> >> + Say Y here if your OpenRISC processor features shadowed
> >> + register files. They will in such case be used as a
> >> + scratch reg storage on exception entry.
> >> +
> >> + On SMP systems, this feature is mandatory.
> >> + On a unicore system it's safe to say N here if you are unsure.
> >> +
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
2017-08-30 21:58 ` [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
@ 2017-08-30 21:58 ` Stafford Horne
2017-09-01 8:06 ` [OpenRISC] " Geert Uytterhoeven
2017-08-30 21:58 ` [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
` (10 subsequent siblings)
12 siblings, 1 reply; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 21:58 UTC (permalink / raw)
To: LKML; +Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson
While working on SMP for OpenRISC I found this is needed for qrwlocks to
work correctly. OpenRISC is big endian so this should have been here
already.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index ba8ae92ec5fb..8ddfc92ab813 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -29,6 +29,9 @@ config OPENRISC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select NO_BOOTMEM
+config CPU_BIG_ENDIAN
+ def_bool y
+
config MMU
def_bool y
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true
2017-08-30 21:58 ` [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne
@ 2017-09-01 8:06 ` Geert Uytterhoeven
2017-09-01 8:28 ` Stafford Horne
0 siblings, 1 reply; 34+ messages in thread
From: Geert Uytterhoeven @ 2017-09-01 8:06 UTC (permalink / raw)
To: Stafford Horne; +Cc: LKML, Jonas Bonn, Openrisc
On Wed, Aug 30, 2017 at 11:58 PM, Stafford Horne <shorne@gmail.com> wrote:
> While working on SMP for OpenRISC I found this is needed for qrwlocks to
> work correctly. OpenRISC is big endian so this should have been here
> already.
>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> arch/openrisc/Kconfig | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> index ba8ae92ec5fb..8ddfc92ab813 100644
> --- a/arch/openrisc/Kconfig
> +++ b/arch/openrisc/Kconfig
> @@ -29,6 +29,9 @@ config OPENRISC
> select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
> select NO_BOOTMEM
>
> +config CPU_BIG_ENDIAN
> + def_bool y
> +
This is already in Andrew's tree and linux-next, as part of commit
410ae809fee6c792 ("arch: define CPU_BIG_ENDIAN for all fixed big endian
archs").
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [OpenRISC] [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true
2017-09-01 8:06 ` [OpenRISC] " Geert Uytterhoeven
@ 2017-09-01 8:28 ` Stafford Horne
0 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-09-01 8:28 UTC (permalink / raw)
To: Geert Uytterhoeven; +Cc: LKML, Jonas Bonn, Openrisc
On Fri, Sep 01, 2017 at 10:06:49AM +0200, Geert Uytterhoeven wrote:
> On Wed, Aug 30, 2017 at 11:58 PM, Stafford Horne <shorne@gmail.com> wrote:
> > While working on SMP for OpenRISC I found this is needed for qrwlocks to
> > work correctly. OpenRISC is big endian so this should have been here
> > already.
> >
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> > arch/openrisc/Kconfig | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> > index ba8ae92ec5fb..8ddfc92ab813 100644
> > --- a/arch/openrisc/Kconfig
> > +++ b/arch/openrisc/Kconfig
> > @@ -29,6 +29,9 @@ config OPENRISC
> > select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
> > select NO_BOOTMEM
> >
> > +config CPU_BIG_ENDIAN
> > + def_bool y
> > +
>
> This is already in Andrew's tree and linux-next, as part of commit
> 410ae809fee6c792 ("arch: define CPU_BIG_ENDIAN for all fixed big endian
> archs").
Thank you, Yes I am cc'd on those patches. I had added this patch myself
some time before 10ae809fee6c792 ("arch: define CPU_BIG_ENDIAN for all
fixed big endian archs") appeared.
Once that gets merged I will rebase and this will disappear.
-Stafford
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
2017-08-30 21:58 ` [PATCH 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-08-30 21:58 ` [PATCH 02/13] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne
@ 2017-08-30 21:58 ` Stafford Horne
2017-08-31 7:46 ` Peter Zijlstra
2017-08-30 21:58 ` [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
` (9 subsequent siblings)
12 siblings, 1 reply; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 21:58 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Peter Zijlstra, Jonas Bonn,
Stefan Kristiansson
OpenRISC only supports hardware instructions that perform 4 byte atomic
operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte
implementations are needed. To do this we leverage the 4 byte atomic
operations and shift/mask the 1 and 2 byte areas as needed.
This heavily borrows ideas and routines from sh and mips, which do
something similar.
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/include/asm/cmpxchg.h | 147 ++++++++++++++++++++++++++++--------
1 file changed, 115 insertions(+), 32 deletions(-)
diff --git a/arch/openrisc/include/asm/cmpxchg.h b/arch/openrisc/include/asm/cmpxchg.h
index f0a5d8b844d6..d29f7db53906 100644
--- a/arch/openrisc/include/asm/cmpxchg.h
+++ b/arch/openrisc/include/asm/cmpxchg.h
@@ -1,32 +1,29 @@
/*
+ * 1,2 and 4 byte cmpxchg and xchg implementations for OpenRISC.
+ *
* Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
+ *
+ * Note:
+ * The portable implementations of 1 and 2 byte xchg and cmpxchg using a 4
+ * byte cmpxchg is sourced heavily from the sh and mips implementations.
*/
#ifndef __ASM_OPENRISC_CMPXCHG_H
#define __ASM_OPENRISC_CMPXCHG_H
#include <linux/types.h>
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg().
- */
-extern void __cmpxchg_called_with_bad_pointer(void);
+#include <linux/bitops.h>
#define __HAVE_ARCH_CMPXCHG 1
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+static inline unsigned long cmpxchg_u32(volatile void *ptr,
+ unsigned long old, unsigned long new)
{
- if (size != 4) {
- __cmpxchg_called_with_bad_pointer();
- return old;
- }
-
__asm__ __volatile__(
"1: l.lwa %0, 0(%1) \n"
" l.sfeq %0, %2 \n"
@@ -43,6 +40,97 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
return old;
}
+static inline unsigned long xchg_u32(volatile void *ptr,
+ unsigned long val)
+{
+ __asm__ __volatile__(
+ "1: l.lwa %0, 0(%1) \n"
+ " l.swa 0(%1), %2 \n"
+ " l.bnf 1b \n"
+ " l.nop \n"
+ : "=&r"(val)
+ : "r"(ptr), "r"(val)
+ : "cc", "memory");
+
+ return val;
+}
+
+static inline u32 cmpxchg_small(volatile void *ptr, u32 old, u32 new,
+ int size)
+{
+ int off = (unsigned long)ptr % sizeof(u32);
+ volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+ int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+ int bitoff = off * BITS_PER_BYTE;
+#endif
+ u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+ u32 load32, old32, new32;
+ u32 ret;
+
+ load32 = READ_ONCE(*p);
+
+ while (true) {
+ ret = (load32 & bitmask) >> bitoff;
+ if (old != ret)
+ return ret;
+
+ old32 = (load32 & ~bitmask) | (old << bitoff);
+ new32 = (load32 & ~bitmask) | (new << bitoff);
+
+ /* Do 32 bit cmpxchg */
+ load32 = cmpxchg_u32(p, old32, new32);
+ if (load32 == old32)
+ return old;
+ }
+}
+
+/* xchg */
+
+static inline u32 xchg_small(volatile void *ptr, u32 x, int size)
+{
+ int off = (unsigned long)ptr % sizeof(u32);
+ volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+ int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+ int bitoff = off * BITS_PER_BYTE;
+#endif
+ u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+ u32 oldv, newv;
+ u32 ret;
+
+ do {
+ oldv = READ_ONCE(*p);
+ ret = (oldv & bitmask) >> bitoff;
+ newv = (oldv & ~bitmask) | (x << bitoff);
+ } while (cmpxchg_u32(p, oldv, newv) != oldv);
+
+ return ret;
+}
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern unsigned long __cmpxchg_called_with_bad_pointer(void)
+ __compiletime_error("Bad argument size for cmpxchg");
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+ unsigned long new, int size)
+{
+ switch (size) {
+ case 1:
+ case 2:
+ return cmpxchg_small(ptr, old, new, size);
+ case 4:
+ return cmpxchg_u32(ptr, old, new);
+ default:
+ return __cmpxchg_called_with_bad_pointer();
+ }
+}
+
#define cmpxchg(ptr, o, n) \
({ \
(__typeof__(*(ptr))) __cmpxchg((ptr), \
@@ -55,32 +143,27 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
* This function doesn't exist, so you'll get a linker error if
* something tries to do an invalidly-sized xchg().
*/
-extern void __xchg_called_with_bad_pointer(void);
+extern unsigned long __xchg_called_with_bad_pointer(void)
+ __compiletime_error("Bad argument size for xchg");
-static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
- int size)
+static inline unsigned long __xchg(volatile void *ptr, unsigned long with,
+ int size)
{
- if (size != 4) {
- __xchg_called_with_bad_pointer();
- return val;
+ switch (size) {
+ case 1:
+ case 2:
+ return xchg_small(ptr, with, size);
+ case 4:
+ return xchg_u32(ptr, with);
+ default:
+ return __xchg_called_with_bad_pointer();
}
-
- __asm__ __volatile__(
- "1: l.lwa %0, 0(%1) \n"
- " l.swa 0(%1), %2 \n"
- " l.bnf 1b \n"
- " l.nop \n"
- : "=&r"(val)
- : "r"(ptr), "r"(val)
- : "cc", "memory");
-
- return val;
}
#define xchg(ptr, with) \
({ \
- (__typeof__(*(ptr))) __xchg((unsigned long)(with), \
- (ptr), \
+ (__typeof__(*(ptr))) __xchg((ptr), \
+ (unsigned long)(with), \
sizeof(*(ptr))); \
})
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support
2017-08-30 21:58 ` [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
@ 2017-08-31 7:46 ` Peter Zijlstra
2017-08-31 9:01 ` Stafford Horne
0 siblings, 1 reply; 34+ messages in thread
From: Peter Zijlstra @ 2017-08-31 7:46 UTC (permalink / raw)
To: Stafford Horne; +Cc: LKML, Openrisc, Jonas Bonn, Stefan Kristiansson
On Thu, Aug 31, 2017 at 06:58:34AM +0900, Stafford Horne wrote:
> OpenRISC only supports hardware instructions that perform 4 byte atomic
> operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte
> implementations are needed. To do this we leverage the 4 byte atomic
> operations and shift/mask the 1 and 2 byte areas as needed.
>
> This heavily borrows ideas and routines from sh and mips, which do
> something similar.
Is there value in lifting them into something common?
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support
2017-08-31 7:46 ` Peter Zijlstra
@ 2017-08-31 9:01 ` Stafford Horne
0 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-31 9:01 UTC (permalink / raw)
To: Peter Zijlstra; +Cc: LKML, Openrisc, Jonas Bonn, Stefan Kristiansson
On Thu, Aug 31, 2017 at 09:46:54AM +0200, Peter Zijlstra wrote:
> On Thu, Aug 31, 2017 at 06:58:34AM +0900, Stafford Horne wrote:
> > OpenRISC only supports hardware instructions that perform 4 byte atomic
> > operations. For enabling qrwlocks for upcoming SMP support 1 and 2 byte
> > implementations are needed. To do this we leverage the 4 byte atomic
> > operations and shift/mask the 1 and 2 byte areas as needed.
> >
> > This heavily borrows ideas and routines from sh and mips, which do
> > something similar.
>
> Is there value in lifting them into something common?
Actually, I was planning on that as a followup patch series.
Also, the timer sync patch [13/13] could me made common which is on my todo
list.
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 04/13] openrisc: use qspinlocks and qrwlocks
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (2 preceding siblings ...)
2017-08-30 21:58 ` [PATCH 03/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
@ 2017-08-30 21:58 ` Stafford Horne
2017-08-30 21:58 ` [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne
` (8 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 21:58 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson,
Peter Zijlstra, Ingo Molnar, Masahiro Yamada, Luis R. Rodriguez,
Jan Henrik Weinstock, Frederic Weisbecker, Al Viro,
Nicolas Dichtel
Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 2 ++
arch/openrisc/include/asm/Kbuild | 4 ++++
arch/openrisc/include/asm/spinlock.h | 12 +++++++++++-
arch/openrisc/include/asm/spinlock_types.h | 7 +++++++
4 files changed, 24 insertions(+), 1 deletion(-)
create mode 100644 arch/openrisc/include/asm/spinlock_types.h
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 8ddfc92ab813..214c837ce597 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -28,6 +28,8 @@ config OPENRISC
select OR1K_PIC
select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
select NO_BOOTMEM
+ select ARCH_USE_QUEUED_SPINLOCKS
+ select ARCH_USE_QUEUED_RWLOCKS
config CPU_BIG_ENDIAN
def_bool y
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5bea416a7792..5f066780d870 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -28,6 +28,10 @@ generic-y += module.h
generic-y += pci.h
generic-y += percpu.h
generic-y += preempt.h
+generic-y += qspinlock_types.h
+generic-y += qspinlock.h
+generic-y += qrwlock_types.h
+generic-y += qrwlock.h
generic-y += sections.h
generic-y += segment.h
generic-y += string.h
diff --git a/arch/openrisc/include/asm/spinlock.h b/arch/openrisc/include/asm/spinlock.h
index fd00a3a24123..9b761e0e22c3 100644
--- a/arch/openrisc/include/asm/spinlock.h
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -19,6 +19,16 @@
#ifndef __ASM_OPENRISC_SPINLOCK_H
#define __ASM_OPENRISC_SPINLOCK_H
-#error "or32 doesn't do SMP yet"
+#include <asm/qspinlock.h>
+
+#include <asm/qrwlock.h>
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock) cpu_relax()
+#define arch_read_relax(lock) cpu_relax()
+#define arch_write_relax(lock) cpu_relax()
+
#endif
diff --git a/arch/openrisc/include/asm/spinlock_types.h b/arch/openrisc/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..7c6fb1208c88
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock_types.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
+#define _ASM_OPENRISC_SPINLOCK_TYPES_H
+
+#include <asm/qspinlock_types.h>
+#include <asm/qrwlock_types.h>
+
+#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 05/13] irqchip: add initial support for ompic
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (3 preceding siblings ...)
2017-08-30 21:58 ` [PATCH 04/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
@ 2017-08-30 21:58 ` Stafford Horne
2017-08-31 9:28 ` Marc Zyngier
2017-08-31 10:59 ` Mark Rutland
2017-08-30 21:58 ` [PATCH 06/13] openrisc: initial SMP support Stafford Horne
` (7 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 21:58 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stefan Kristiansson, Stafford Horne, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Mark Rutland, Jonas Bonn,
devicetree
From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
IPI driver for OpenRISC Multicore programmable interrupt controller as
described in the Multicore support section of the OpenRISC 1.2
proposed architecture specification:
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing. This IPI device is the
only external device required for enabling SMP on OpenRISC.
Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
.../bindings/interrupt-controller/ompic.txt | 22 ++++
arch/openrisc/Kconfig | 1 +
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++
5 files changed, 145 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt
create mode 100644 drivers/irqchip/irq-ompic.c
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
new file mode 100644
index 000000000000..4176ecc3366d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
@@ -0,0 +1,22 @@
+OpenRISC Multicore Programmable Interrupt Controller
+
+Required properties:
+
+- compatible : This should be "ompic"
+- reg : Specifies base physical address and size of the register space. The
+ size can be arbitrary based on the number of cores the controller has
+ been configured to handle, typically 8 bytes per core.
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1.
+- interrupts : Specifies the interrupt line to which the ompic is wired.
+
+Example:
+
+ompic: ompic {
+ compatible = "ompic";
+ reg = <0x98000000 16>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <1>;
+};
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 214c837ce597..dd7e55e7e42d 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -30,6 +30,7 @@ config OPENRISC
select NO_BOOTMEM
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
+ select OMPIC if SMP
config CPU_BIG_ENDIAN
def_bool y
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f1fd5f44d1d4..3fa60e6667a7 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -145,6 +145,10 @@ config CLPS711X_IRQCHIP
select SPARSE_IRQ
default y
+config OMPIC
+ bool
+ select IRQ_DOMAIN
+
config OR1K_PIC
bool
select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e88d856cc09c..123047d7a20d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
+obj-$(CONFIG_OMPIC) += irq-ompic.o
obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
new file mode 100644
index 000000000000..438819f8a5a7
--- /dev/null
+++ b/drivers/irqchip/irq-ompic.c
@@ -0,0 +1,117 @@
+/*
+ * Open Multi-Processor Interrupt Controller driver
+ *
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/irqchip/chained_irq.h>
+#include <linux/delay.h>
+
+#include <linux/irqchip.h>
+
+#define OMPIC_IPI_BASE 0x0
+#define OMPIC_IPI_CTRL(cpu) (OMPIC_IPI_BASE + 0x0 + (cpu)*8)
+#define OMPIC_IPI_STAT(cpu) (OMPIC_IPI_BASE + 0x4 + (cpu)*8)
+
+#define OMPIC_IPI_CTRL_IRQ_ACK (1 << 31)
+#define OMPIC_IPI_CTRL_IRQ_GEN (1 << 30)
+#define OMPIC_IPI_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
+
+#define OMPIC_IPI_STAT_IRQ_PENDING (1 << 30)
+
+#define OMPIC_IPI_DATA(x) ((x) & 0xffff)
+
+static struct {
+ unsigned long ops;
+} ipi_data[NR_CPUS];
+
+static void __iomem *ompic_base;
+
+static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
+{
+ return ioread32be(base + offset);
+}
+
+static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
+{
+ iowrite32be(data, base + offset);
+}
+
+#ifdef CONFIG_SMP
+void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)
+{
+ unsigned int dst_cpu;
+ unsigned int src_cpu = smp_processor_id();
+
+ for_each_cpu(dst_cpu, mask) {
+ set_bit(irq, &ipi_data[dst_cpu].ops);
+
+ ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
+ OMPIC_IPI_CTRL_IRQ_GEN |
+ OMPIC_IPI_CTRL_DST(dst_cpu) |
+ OMPIC_IPI_DATA(1));
+ }
+}
+#endif
+
+irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
+{
+ unsigned int cpu = smp_processor_id();
+ unsigned long *pending_ops = &ipi_data[cpu].ops;
+ unsigned long ops;
+
+ ompic_writereg(ompic_base, OMPIC_IPI_CTRL(cpu), OMPIC_IPI_CTRL_IRQ_ACK);
+ while ((ops = xchg(pending_ops, 0)) != 0) {
+ do {
+ unsigned long ipi;
+
+ ipi = ops & -ops;
+ ops &= ~ipi;
+ ipi = __ffs(ipi);
+
+ handle_IPI(ipi);
+ } while (ops);
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction ompi_ipi_irqaction = {
+ .handler = ompic_ipi_handler,
+ .flags = IRQF_PERCPU,
+ .name = "ompic_ipi",
+};
+
+#ifdef CONFIG_OF
+int __init ompic_of_init(struct device_node *node, struct device_node *parent)
+{
+ int irq;
+
+ if (WARN_ON(!node))
+ return -ENODEV;
+
+ memset(ipi_data, 0, sizeof(ipi_data));
+
+ ompic_base = of_iomap(node, 0);
+
+ irq = irq_of_parse_and_map(node, 0);
+ setup_irq(irq, &ompi_ipi_irqaction);
+
+#ifdef CONFIG_SMP
+ set_smp_cross_call(ompic_raise_softirq);
+#endif
+
+ return 0;
+}
+IRQCHIP_DECLARE(ompic, "ompic", ompic_of_init);
+#endif
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH 05/13] irqchip: add initial support for ompic
2017-08-30 21:58 ` [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne
@ 2017-08-31 9:28 ` Marc Zyngier
2017-09-01 1:24 ` Stafford Horne
2017-08-31 10:59 ` Mark Rutland
1 sibling, 1 reply; 34+ messages in thread
From: Marc Zyngier @ 2017-08-31 9:28 UTC (permalink / raw)
To: Stafford Horne, LKML
Cc: Openrisc, Stefan Kristiansson, Thomas Gleixner, Jason Cooper,
Rob Herring, Mark Rutland, Jonas Bonn, devicetree
On 30/08/17 22:58, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> IPI driver for OpenRISC Multicore programmable interrupt controller as
> described in the Multicore support section of the OpenRISC 1.2
> proposed architecture specification:
>
> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing. This IPI device is the
> only external device required for enabling SMP on OpenRISC.
>
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> .../bindings/interrupt-controller/ompic.txt | 22 ++++
> arch/openrisc/Kconfig | 1 +
> drivers/irqchip/Kconfig | 4 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++
> 5 files changed, 145 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> create mode 100644 drivers/irqchip/irq-ompic.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> new file mode 100644
> index 000000000000..4176ecc3366d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> @@ -0,0 +1,22 @@
> +OpenRISC Multicore Programmable Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : This should be "ompic"
> +- reg : Specifies base physical address and size of the register space. The
> + size can be arbitrary based on the number of cores the controller has
> + been configured to handle, typically 8 bytes per core.
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 1.
> +- interrupts : Specifies the interrupt line to which the ompic is wired.
> +
> +Example:
> +
> +ompic: ompic {
> + compatible = "ompic";
> + reg = <0x98000000 16>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupts = <1>;
> +};
> diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> index 214c837ce597..dd7e55e7e42d 100644
> --- a/arch/openrisc/Kconfig
> +++ b/arch/openrisc/Kconfig
> @@ -30,6 +30,7 @@ config OPENRISC
> select NO_BOOTMEM
> select ARCH_USE_QUEUED_SPINLOCKS
> select ARCH_USE_QUEUED_RWLOCKS
> + select OMPIC if SMP
>
> config CPU_BIG_ENDIAN
> def_bool y
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index f1fd5f44d1d4..3fa60e6667a7 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -145,6 +145,10 @@ config CLPS711X_IRQCHIP
> select SPARSE_IRQ
> default y
>
> +config OMPIC
> + bool
> + select IRQ_DOMAIN
Why do you need to select IRQ_DOMAIN? This driver doesn't seem to use any...
> +
> config OR1K_PIC
> bool
> select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index e88d856cc09c..123047d7a20d 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
> obj-$(CONFIG_METAG) += irq-metag-ext.o
> obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
> obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
> +obj-$(CONFIG_OMPIC) += irq-ompic.o
> obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
> obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
> obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
> diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
> new file mode 100644
> index 000000000000..438819f8a5a7
> --- /dev/null
> +++ b/drivers/irqchip/irq-ompic.c
> @@ -0,0 +1,117 @@
> +/*
> + * Open Multi-Processor Interrupt Controller driver
> + *
> + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2. This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/smp.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +#include <linux/irqchip/chained_irq.h>
Don't think you need this.
> +#include <linux/delay.h>
Nor this.
> +
> +#include <linux/irqchip.h>
> +
> +#define OMPIC_IPI_BASE 0x0
> +#define OMPIC_IPI_CTRL(cpu) (OMPIC_IPI_BASE + 0x0 + (cpu)*8)
> +#define OMPIC_IPI_STAT(cpu) (OMPIC_IPI_BASE + 0x4 + (cpu)*8)
In the DT binding you say that "size can be arbitrary based on the
number of cores the controller has been configured to handle, typically
8 bytes per core". Here, this is 8 bytes, always, which is not exactly
the same. What is the architectural value, if any? If there is none,
then the per-core size should either come from DT or some other mean
(register?).
> +
> +#define OMPIC_IPI_CTRL_IRQ_ACK (1 << 31)
> +#define OMPIC_IPI_CTRL_IRQ_GEN (1 << 30)
> +#define OMPIC_IPI_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
> +
> +#define OMPIC_IPI_STAT_IRQ_PENDING (1 << 30)
> +
> +#define OMPIC_IPI_DATA(x) ((x) & 0xffff)
> +
> +static struct {
> + unsigned long ops;
> +} ipi_data[NR_CPUS];
In general, a per cpu data structure is better expressed as a percpu
data structure (yes, I'm in a funny mood this morning). Otherwise,
you're going to thrash more than just the receiver and the sender, but
also all the other CPUs that have their data in the same cache line.
> +
> +static void __iomem *ompic_base;
> +
> +static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
> +{
> + return ioread32be(base + offset);
> +}
> +
> +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
> +{
> + iowrite32be(data, base + offset);
> +}
> +
> +#ifdef CONFIG_SMP
This code is only selected when CONFIG_SMP=y.
> +void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)
> +{
What is "irq" here? How is it guaranteed to fit in an unsigned long?
> + unsigned int dst_cpu;
> + unsigned int src_cpu = smp_processor_id();
> +
> + for_each_cpu(dst_cpu, mask) {
> + set_bit(irq, &ipi_data[dst_cpu].ops);
> +
> + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
> + OMPIC_IPI_CTRL_IRQ_GEN |
> + OMPIC_IPI_CTRL_DST(dst_cpu) |
> + OMPIC_IPI_DATA(1));
What guarantees that the action of set_bit can be observed by the target
CPU? set-bit gives you atomicity, but no barrier.
> + }
> +}
> +#endif
> +
> +irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
> +{
> + unsigned int cpu = smp_processor_id();
> + unsigned long *pending_ops = &ipi_data[cpu].ops;
> + unsigned long ops;
> +
> + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(cpu), OMPIC_IPI_CTRL_IRQ_ACK);
> + while ((ops = xchg(pending_ops, 0)) != 0) {
Barrier again?
> + do {
> + unsigned long ipi;
> +
> + ipi = ops & -ops;
> + ops &= ~ipi;
> + ipi = __ffs(ipi);
This feels pointlessly convoluted. Is there any reason why you can't
write it as:
ipi = __ffs(ops);
ops &= ~(1UL << ipi);
which feels like a much more common idiom?
> +
> + handle_IPI(ipi);
> + } while (ops);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static struct irqaction ompi_ipi_irqaction = {
> + .handler = ompic_ipi_handler,
> + .flags = IRQF_PERCPU,
> + .name = "ompic_ipi",
> +};
> +
> +#ifdef CONFIG_OF
This code is useless if you don't have CONFIG_OF. So either you make the
driver depend on CONFIG_OF, or you actively select it. And given that
CONFIG_OPENRISC already selects CONFIG_OF, you can happily get rid of
all the #ifdefery here.
> +int __init ompic_of_init(struct device_node *node, struct device_node *parent)
> +{
> + int irq;
> +
> + if (WARN_ON(!node))
> + return -ENODEV;
How do you end-up here if node == NULL?
> +
> + memset(ipi_data, 0, sizeof(ipi_data));
The kernel should do this for you already.
> +
> + ompic_base = of_iomap(node, 0);
> +
> + irq = irq_of_parse_and_map(node, 0);
> + setup_irq(irq, &ompi_ipi_irqaction);
> +
> +#ifdef CONFIG_SMP
> + set_smp_cross_call(ompic_raise_softirq);
> +#endif
> +
> + return 0;
> +}
> +IRQCHIP_DECLARE(ompic, "ompic", ompic_of_init);
> +#endif
>
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 05/13] irqchip: add initial support for ompic
2017-08-31 9:28 ` Marc Zyngier
@ 2017-09-01 1:24 ` Stafford Horne
2017-09-01 17:25 ` Marc Zyngier
0 siblings, 1 reply; 34+ messages in thread
From: Stafford Horne @ 2017-09-01 1:24 UTC (permalink / raw)
To: Marc Zyngier
Cc: LKML, Openrisc, Stefan Kristiansson, Thomas Gleixner,
Jason Cooper, Rob Herring, Mark Rutland, Jonas Bonn, devicetree
On Thu, Aug 31, 2017 at 10:28:01AM +0100, Marc Zyngier wrote:
> On 30/08/17 22:58, Stafford Horne wrote:
> > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >
> > IPI driver for OpenRISC Multicore programmable interrupt controller as
> > described in the Multicore support section of the OpenRISC 1.2
> > proposed architecture specification:
> >
> > https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
> >
> > Each OpenRISC core contains a full interrupt controller which is used in
> > the SMP architecture for interrupt balancing. This IPI device is the
> > only external device required for enabling SMP on OpenRISC.
> >
> > Pending ops are stored in a memory bit mask which can allow multiple
> > pending operations to be set and serviced at a time. This is mostly
> > borrowed from the alpha IPI implementation.
> >
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> > .../bindings/interrupt-controller/ompic.txt | 22 ++++
> > arch/openrisc/Kconfig | 1 +
> > drivers/irqchip/Kconfig | 4 +
> > drivers/irqchip/Makefile | 1 +
> > drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++
> > 5 files changed, 145 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> > create mode 100644 drivers/irqchip/irq-ompic.c
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> > new file mode 100644
> > index 000000000000..4176ecc3366d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> > @@ -0,0 +1,22 @@
> > +OpenRISC Multicore Programmable Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible : This should be "ompic"
> > +- reg : Specifies base physical address and size of the register space. The
> > + size can be arbitrary based on the number of cores the controller has
> > + been configured to handle, typically 8 bytes per core.
> > +- interrupt-controller : Identifies the node as an interrupt controller
> > +- #interrupt-cells : Specifies the number of cells needed to encode an
> > + interrupt source. The value shall be 1.
> > +- interrupts : Specifies the interrupt line to which the ompic is wired.
> > +
> > +Example:
> > +
> > +ompic: ompic {
> > + compatible = "ompic";
> > + reg = <0x98000000 16>;
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + interrupts = <1>;
> > +};
> > diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> > index 214c837ce597..dd7e55e7e42d 100644
> > --- a/arch/openrisc/Kconfig
> > +++ b/arch/openrisc/Kconfig
> > @@ -30,6 +30,7 @@ config OPENRISC
> > select NO_BOOTMEM
> > select ARCH_USE_QUEUED_SPINLOCKS
> > select ARCH_USE_QUEUED_RWLOCKS
> > + select OMPIC if SMP
> >
> > config CPU_BIG_ENDIAN
> > def_bool y
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index f1fd5f44d1d4..3fa60e6667a7 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -145,6 +145,10 @@ config CLPS711X_IRQCHIP
> > select SPARSE_IRQ
> > default y
> >
> > +config OMPIC
> > + bool
> > + select IRQ_DOMAIN
>
> Why do you need to select IRQ_DOMAIN? This driver doesn't seem to use any...
Right, I will look to remove that.
> > +
> > config OR1K_PIC
> > bool
> > select IRQ_DOMAIN
> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> > index e88d856cc09c..123047d7a20d 100644
> > --- a/drivers/irqchip/Makefile
> > +++ b/drivers/irqchip/Makefile
> > @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
> > obj-$(CONFIG_METAG) += irq-metag-ext.o
> > obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
> > obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
> > +obj-$(CONFIG_OMPIC) += irq-ompic.o
> > obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
> > obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
> > obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
> > diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
> > new file mode 100644
> > index 000000000000..438819f8a5a7
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-ompic.c
> > @@ -0,0 +1,117 @@
> > +/*
> > + * Open Multi-Processor Interrupt Controller driver
> > + *
> > + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > + *
> > + * This file is licensed under the terms of the GNU General Public License
> > + * version 2. This program is licensed "as is" without any warranty of any
> > + * kind, whether express or implied.
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/smp.h>
> > +#include <linux/of.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_address.h>
> > +#include <linux/irqchip/chained_irq.h>
>
> Don't think you need this.
>
> > +#include <linux/delay.h>
>
> Nor this.
OK on both.
> > +
> > +#include <linux/irqchip.h>
> > +
> > +#define OMPIC_IPI_BASE 0x0
> > +#define OMPIC_IPI_CTRL(cpu) (OMPIC_IPI_BASE + 0x0 + (cpu)*8)
> > +#define OMPIC_IPI_STAT(cpu) (OMPIC_IPI_BASE + 0x4 + (cpu)*8)
>
> In the DT binding you say that "size can be arbitrary based on the
> number of cores the controller has been configured to handle, typically
> 8 bytes per core". Here, this is 8 bytes, always, which is not exactly
> the same. What is the architectural value, if any? If there is none,
> then the per-core size should either come from DT or some other mean
> (register?).
I mean the address space is 8 bytes x number-of-cores. Thats what I meant
by arbitrary, I guess its better for me to be explicit. There is no
register that we can check to confirm the configuration of ompic. But I
guess we can check the CPU NUMCORES register and compare it to the DT
address space to do a sanity check.
> > +
> > +#define OMPIC_IPI_CTRL_IRQ_ACK (1 << 31)
> > +#define OMPIC_IPI_CTRL_IRQ_GEN (1 << 30)
> > +#define OMPIC_IPI_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
> > +
> > +#define OMPIC_IPI_STAT_IRQ_PENDING (1 << 30)
> > +
> > +#define OMPIC_IPI_DATA(x) ((x) & 0xffff)
> > +
> > +static struct {
> > + unsigned long ops;
> > +} ipi_data[NR_CPUS];
>
> In general, a per cpu data structure is better expressed as a percpu
> data structure (yes, I'm in a funny mood this morning). Otherwise,
> you're going to thrash more than just the receiver and the sender, but
> also all the other CPUs that have their data in the same cache line.
Right, that makes sense, I am not sure why that was done this way. I think
I borrowed from alpha which has the extra __cacheline_aligned annotations.
I forgot to come back and fix this. Ill do as you suggest, thank you.
Excerpt from alpha:
static struct {
unsigned long bits ____cacheline_aligned;
} ipi_data[NR_CPUS] __cacheline_aligned;
> > +
> > +static void __iomem *ompic_base;
> > +
> > +static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
> > +{
> > + return ioread32be(base + offset);
> > +}
> > +
> > +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
> > +{
> > + iowrite32be(data, base + offset);
> > +}
> > +
> > +#ifdef CONFIG_SMP
>
> This code is only selected when CONFIG_SMP=y.
Yes, that is right, as below:
set_smp_cross_call(ompic_raise_softirq);
The set_smp_cross_call() function from smp.c is only defined for smp. Do
you think thats wrong or needed extra comments? This is similar to other
chips in irqchip/ for archs which use set_smp_cross_call().
> > +void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)
> > +{
>
> What is "irq" here? How is it guaranteed to fit in an unsigned long?
Here irq is the `enum ipi_msg_type` which is guaranteed to fit in unsigned
long. Porbably its better to rename as msg or ipi_msg?
> > + unsigned int dst_cpu;
> > + unsigned int src_cpu = smp_processor_id();
> > +
> > + for_each_cpu(dst_cpu, mask) {
> > + set_bit(irq, &ipi_data[dst_cpu].ops);
> > +
> > + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
> > + OMPIC_IPI_CTRL_IRQ_GEN |
> > + OMPIC_IPI_CTRL_DST(dst_cpu) |
> > + OMPIC_IPI_DATA(1));
>
> What guarantees that the action of set_bit can be observed by the target
> CPU? set-bit gives you atomicity, but no barrier.
The bit will not be read by target CPUs until after the ompic_writereg()
which will trigger the target CPU interrupt to be raised. OpenRISC stores
are ordered.
This will work on OpenRISC, but should I be thinking of other architectures
as well for all drivers? Or do you think this will be an issue on
OpenRISC?
> > + }
> > +}
> > +#endif
> > +
> > +irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
> > +{
> > + unsigned int cpu = smp_processor_id();
> > + unsigned long *pending_ops = &ipi_data[cpu].ops;
> > + unsigned long ops;
> > +
> > + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(cpu), OMPIC_IPI_CTRL_IRQ_ACK);
> > + while ((ops = xchg(pending_ops, 0)) != 0) {
>
> Barrier again?
Thanks, but some concern of above.
> > + do {
> > + unsigned long ipi;
> > +
> > + ipi = ops & -ops;
> > + ops &= ~ipi;
> > + ipi = __ffs(ipi);
>
> This feels pointlessly convoluted. Is there any reason why you can't
> write it as:
>
> ipi = __ffs(ops);
> ops &= ~(1UL << ipi);
>
> which feels like a much more common idiom?
Right, this should work, not sure what I was thinking above right now. Let
me give that a try.
> > +
> > + handle_IPI(ipi);
> > + } while (ops);
> > + }
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static struct irqaction ompi_ipi_irqaction = {
> > + .handler = ompic_ipi_handler,
> > + .flags = IRQF_PERCPU,
> > + .name = "ompic_ipi",
> > +};
> > +
> > +#ifdef CONFIG_OF
>
> This code is useless if you don't have CONFIG_OF. So either you make the
> driver depend on CONFIG_OF, or you actively select it. And given that
> CONFIG_OPENRISC already selects CONFIG_OF, you can happily get rid of
> all the #ifdefery here.
Thanks, right.
> > +int __init ompic_of_init(struct device_node *node, struct device_node *parent)
> > +{
> > + int irq;
> > +
> > + if (WARN_ON(!node))
> > + return -ENODEV;
>
> How do you end-up here if node == NULL?
Right.
> > +
> > + memset(ipi_data, 0, sizeof(ipi_data));
>
> The kernel should do this for you already.
Right.
> > +
> > + ompic_base = of_iomap(node, 0);
> > +
> > + irq = irq_of_parse_and_map(node, 0);
> > + setup_irq(irq, &ompi_ipi_irqaction);
> > +
> > +#ifdef CONFIG_SMP
> > + set_smp_cross_call(ompic_raise_softirq);
> > +#endif
> > +
> > + return 0;
> > +}
> > +IRQCHIP_DECLARE(ompic, "ompic", ompic_of_init);
> > +#endif
> >
Thank you for the feedback, I will clean this up and resubmit with the
comments on the other thread.
In terms of commit path, do you think its ok for this to go in via the
OpenRISC arch path?
-Stafford
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 05/13] irqchip: add initial support for ompic
2017-09-01 1:24 ` Stafford Horne
@ 2017-09-01 17:25 ` Marc Zyngier
2017-09-03 22:12 ` Stafford Horne
0 siblings, 1 reply; 34+ messages in thread
From: Marc Zyngier @ 2017-09-01 17:25 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Openrisc, Stefan Kristiansson, Thomas Gleixner,
Jason Cooper, Rob Herring, Mark Rutland, Jonas Bonn, devicetree
On 01/09/17 02:24, Stafford Horne wrote:
> On Thu, Aug 31, 2017 at 10:28:01AM +0100, Marc Zyngier wrote:
>> On 30/08/17 22:58, Stafford Horne wrote:
>>> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>>>
>>> IPI driver for OpenRISC Multicore programmable interrupt controller as
>>> described in the Multicore support section of the OpenRISC 1.2
>>> proposed architecture specification:
>>>
>>> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>>>
>>> Each OpenRISC core contains a full interrupt controller which is used in
>>> the SMP architecture for interrupt balancing. This IPI device is the
>>> only external device required for enabling SMP on OpenRISC.
>>>
>>> Pending ops are stored in a memory bit mask which can allow multiple
>>> pending operations to be set and serviced at a time. This is mostly
>>> borrowed from the alpha IPI implementation.
>>>
>>> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>>> [shorne@gmail.com: converted ops to bitmask, wrote commit message]
>>> Signed-off-by: Stafford Horne <shorne@gmail.com>
>>> ---
>>> .../bindings/interrupt-controller/ompic.txt | 22 ++++
>>> arch/openrisc/Kconfig | 1 +
>>> drivers/irqchip/Kconfig | 4 +
>>> drivers/irqchip/Makefile | 1 +
>>> drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++
>>> 5 files changed, 145 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt
>>> create mode 100644 drivers/irqchip/irq-ompic.c
>>>
>>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
>>> new file mode 100644
>>> index 000000000000..4176ecc3366d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
>>> @@ -0,0 +1,22 @@
>>> +OpenRISC Multicore Programmable Interrupt Controller
>>> +
>>> +Required properties:
>>> +
>>> +- compatible : This should be "ompic"
>>> +- reg : Specifies base physical address and size of the register space. The
>>> + size can be arbitrary based on the number of cores the controller has
>>> + been configured to handle, typically 8 bytes per core.
>>> +- interrupt-controller : Identifies the node as an interrupt controller
>>> +- #interrupt-cells : Specifies the number of cells needed to encode an
>>> + interrupt source. The value shall be 1.
>>> +- interrupts : Specifies the interrupt line to which the ompic is wired.
>>> +
>>> +Example:
>>> +
>>> +ompic: ompic {
>>> + compatible = "ompic";
>>> + reg = <0x98000000 16>;
>>> + #interrupt-cells = <1>;
>>> + interrupt-controller;
>>> + interrupts = <1>;
>>> +};
>>> diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
>>> index 214c837ce597..dd7e55e7e42d 100644
>>> --- a/arch/openrisc/Kconfig
>>> +++ b/arch/openrisc/Kconfig
>>> @@ -30,6 +30,7 @@ config OPENRISC
>>> select NO_BOOTMEM
>>> select ARCH_USE_QUEUED_SPINLOCKS
>>> select ARCH_USE_QUEUED_RWLOCKS
>>> + select OMPIC if SMP
>>>
>>> config CPU_BIG_ENDIAN
>>> def_bool y
>>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
>>> index f1fd5f44d1d4..3fa60e6667a7 100644
>>> --- a/drivers/irqchip/Kconfig
>>> +++ b/drivers/irqchip/Kconfig
>>> @@ -145,6 +145,10 @@ config CLPS711X_IRQCHIP
>>> select SPARSE_IRQ
>>> default y
>>>
>>> +config OMPIC
>>> + bool
>>> + select IRQ_DOMAIN
>>
>> Why do you need to select IRQ_DOMAIN? This driver doesn't seem to use any...
>
> Right, I will look to remove that.
>
>>> +
>>> config OR1K_PIC
>>> bool
>>> select IRQ_DOMAIN
>>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
>>> index e88d856cc09c..123047d7a20d 100644
>>> --- a/drivers/irqchip/Makefile
>>> +++ b/drivers/irqchip/Makefile
>>> @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
>>> obj-$(CONFIG_METAG) += irq-metag-ext.o
>>> obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
>>> obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
>>> +obj-$(CONFIG_OMPIC) += irq-ompic.o
>>> obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
>>> obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
>>> obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
>>> diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
>>> new file mode 100644
>>> index 000000000000..438819f8a5a7
>>> --- /dev/null
>>> +++ b/drivers/irqchip/irq-ompic.c
>>> @@ -0,0 +1,117 @@
>>> +/*
>>> + * Open Multi-Processor Interrupt Controller driver
>>> + *
>>> + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>>> + *
>>> + * This file is licensed under the terms of the GNU General Public License
>>> + * version 2. This program is licensed "as is" without any warranty of any
>>> + * kind, whether express or implied.
>>> + */
>>> +
>>> +#include <linux/io.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/smp.h>
>>> +#include <linux/of.h>
>>> +#include <linux/of_irq.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/irqchip/chained_irq.h>
>>
>> Don't think you need this.
>>
>>> +#include <linux/delay.h>
>>
>> Nor this.
>
> OK on both.
>
>>> +
>>> +#include <linux/irqchip.h>
>>> +
>>> +#define OMPIC_IPI_BASE 0x0
>>> +#define OMPIC_IPI_CTRL(cpu) (OMPIC_IPI_BASE + 0x0 + (cpu)*8)
>>> +#define OMPIC_IPI_STAT(cpu) (OMPIC_IPI_BASE + 0x4 + (cpu)*8)
>>
>> In the DT binding you say that "size can be arbitrary based on the
>> number of cores the controller has been configured to handle, typically
>> 8 bytes per core". Here, this is 8 bytes, always, which is not exactly
>> the same. What is the architectural value, if any? If there is none,
>> then the per-core size should either come from DT or some other mean
>> (register?).
>
> I mean the address space is 8 bytes x number-of-cores. Thats what I meant
> by arbitrary, I guess its better for me to be explicit. There is no
> register that we can check to confirm the configuration of ompic. But I
> guess we can check the CPU NUMCORES register and compare it to the DT
> address space to do a sanity check.
Thanks for the explanation. So the code is OK, but the DT should be more
rigorous in saying that there is 8 bytes per CPU. And yes to the check
if that can be done at this stage.
>
>>> +
>>> +#define OMPIC_IPI_CTRL_IRQ_ACK (1 << 31)
>>> +#define OMPIC_IPI_CTRL_IRQ_GEN (1 << 30)
>>> +#define OMPIC_IPI_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
>>> +
>>> +#define OMPIC_IPI_STAT_IRQ_PENDING (1 << 30)
>>> +
>>> +#define OMPIC_IPI_DATA(x) ((x) & 0xffff)
>>> +
>>> +static struct {
>>> + unsigned long ops;
>>> +} ipi_data[NR_CPUS];
>>
>> In general, a per cpu data structure is better expressed as a percpu
>> data structure (yes, I'm in a funny mood this morning). Otherwise,
>> you're going to thrash more than just the receiver and the sender, but
>> also all the other CPUs that have their data in the same cache line.
>
> Right, that makes sense, I am not sure why that was done this way. I think
> I borrowed from alpha which has the extra __cacheline_aligned annotations.
> I forgot to come back and fix this. Ill do as you suggest, thank you.
>
> Excerpt from alpha:
>
> static struct {
> unsigned long bits ____cacheline_aligned;
> } ipi_data[NR_CPUS] __cacheline_aligned;
Yup, __cacheline_aligned is key here, as it will have the same effect as
the percpu stuff from that point of view.
>>> +
>>> +static void __iomem *ompic_base;
>>> +
>>> +static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
>>> +{
>>> + return ioread32be(base + offset);
>>> +}
>>> +
>>> +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
>>> +{
>>> + iowrite32be(data, base + offset);
>>> +}
>>> +
>>> +#ifdef CONFIG_SMP
>>
>> This code is only selected when CONFIG_SMP=y.
>
> Yes, that is right, as below:
>
> set_smp_cross_call(ompic_raise_softirq);
>
> The set_smp_cross_call() function from smp.c is only defined for smp. Do
> you think thats wrong or needed extra comments? This is similar to other
> chips in irqchip/ for archs which use set_smp_cross_call().
Other irqchips can often be compiled for both SMP and !SMP, hence the
need of a #ifdef. In your case, this driver is only compiled when SMP is
selected, so you're pretty much guaranteed that this symbol is available.
>
>>> +void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)
>>> +{
>>
>> What is "irq" here? How is it guaranteed to fit in an unsigned long?
>
> Here irq is the `enum ipi_msg_type` which is guaranteed to fit in unsigned
> long. Porbably its better to rename as msg or ipi_msg?
You should certainly make sure your "enum ipi_msg_type" is capped at the
number of bits of unsigned long. And yes to ipi_msg, which is a better
name than irq. Also, you could change the types of ompic_raise_softirq
and set_smp_cross_call, so that you use the enum instead of an int here.
>
>>> + unsigned int dst_cpu;
>>> + unsigned int src_cpu = smp_processor_id();
>>> +
>>> + for_each_cpu(dst_cpu, mask) {
>>> + set_bit(irq, &ipi_data[dst_cpu].ops);
>>> +
>>> + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
>>> + OMPIC_IPI_CTRL_IRQ_GEN |
>>> + OMPIC_IPI_CTRL_DST(dst_cpu) |
>>> + OMPIC_IPI_DATA(1));
>>
>> What guarantees that the action of set_bit can be observed by the target
>> CPU? set-bit gives you atomicity, but no barrier.
>
> The bit will not be read by target CPUs until after the ompic_writereg()
> which will trigger the target CPU interrupt to be raised. OpenRISC stores
> are ordered.
Are they really ordered irrespective of the memory type (one is
cacheable RAM, the other is a device...)?
And assuming they are (which I find a bit odd), that doesn't necessarily
guarantee that the interrupt will only be delivered once the effect of
set_bit can be seen on the target CPU...
> This will work on OpenRISC, but should I be thinking of other architectures
> as well for all drivers? Or do you think this will be an issue on
> OpenRISC?
I definitely think this could be an issue with OpenRISC, but only
someone familiar with the OpenRISC architecture can say whether I'm
right or wrong. I'm just guessing at the moment.
[...]
> Thank you for the feedback, I will clean this up and resubmit with the
> comments on the other thread.
>
> In terms of commit path, do you think its ok for this to go in via the
> OpenRISC arch path?
Sure, that's fine by me.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 05/13] irqchip: add initial support for ompic
2017-09-01 17:25 ` Marc Zyngier
@ 2017-09-03 22:12 ` Stafford Horne
2017-09-04 7:35 ` Marc Zyngier
0 siblings, 1 reply; 34+ messages in thread
From: Stafford Horne @ 2017-09-03 22:12 UTC (permalink / raw)
To: Marc Zyngier
Cc: LKML, Openrisc, Stefan Kristiansson, Thomas Gleixner,
Jason Cooper, Rob Herring, Mark Rutland, Jonas Bonn, devicetree
On Fri, Sep 01, 2017 at 06:25:01PM +0100, Marc Zyngier wrote:
> On 01/09/17 02:24, Stafford Horne wrote:
> > On Thu, Aug 31, 2017 at 10:28:01AM +0100, Marc Zyngier wrote:
> >> On 30/08/17 22:58, Stafford Horne wrote:
> >>> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >>>
> >>> IPI driver for OpenRISC Multicore programmable interrupt controller as
> >>> described in the Multicore support section of the OpenRISC 1.2
> >>> proposed architecture specification:
> >>>
> >>> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
> >>>
> >>> Each OpenRISC core contains a full interrupt controller which is used in
> >>> the SMP architecture for interrupt balancing. This IPI device is the
> >>> only external device required for enabling SMP on OpenRISC.
> >>>
> >>> Pending ops are stored in a memory bit mask which can allow multiple
> >>> pending operations to be set and serviced at a time. This is mostly
> >>> borrowed from the alpha IPI implementation.
> >>>
> >>> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >>> [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> >>> Signed-off-by: Stafford Horne <shorne@gmail.com>
> >>> ---
> >>> .../bindings/interrupt-controller/ompic.txt | 22 ++++
> >>> arch/openrisc/Kconfig | 1 +
> >>> drivers/irqchip/Kconfig | 4 +
> >>> drivers/irqchip/Makefile | 1 +
> >>> drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++
> >>> 5 files changed, 145 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> >>> create mode 100644 drivers/irqchip/irq-ompic.c
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> >>> new file mode 100644
> >>> index 000000000000..4176ecc3366d
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> >>> @@ -0,0 +1,22 @@
> >>> +OpenRISC Multicore Programmable Interrupt Controller
> >>> +
> >>> +Required properties:
> >>> +
> >>> +- compatible : This should be "ompic"
> >>> +- reg : Specifies base physical address and size of the register space. The
> >>> + size can be arbitrary based on the number of cores the controller has
> >>> + been configured to handle, typically 8 bytes per core.
> >>> +- interrupt-controller : Identifies the node as an interrupt controller
> >>> +- #interrupt-cells : Specifies the number of cells needed to encode an
> >>> + interrupt source. The value shall be 1.
> >>> +- interrupts : Specifies the interrupt line to which the ompic is wired.
> >>> +
> >>> +Example:
> >>> +
> >>> +ompic: ompic {
> >>> + compatible = "ompic";
> >>> + reg = <0x98000000 16>;
> >>> + #interrupt-cells = <1>;
> >>> + interrupt-controller;
> >>> + interrupts = <1>;
> >>> +};
> >>> diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> >>> index 214c837ce597..dd7e55e7e42d 100644
> >>> --- a/arch/openrisc/Kconfig
> >>> +++ b/arch/openrisc/Kconfig
> >>> @@ -30,6 +30,7 @@ config OPENRISC
> >>> select NO_BOOTMEM
> >>> select ARCH_USE_QUEUED_SPINLOCKS
> >>> select ARCH_USE_QUEUED_RWLOCKS
> >>> + select OMPIC if SMP
> >>>
> >>> config CPU_BIG_ENDIAN
> >>> def_bool y
> >>> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> >>> index f1fd5f44d1d4..3fa60e6667a7 100644
> >>> --- a/drivers/irqchip/Kconfig
> >>> +++ b/drivers/irqchip/Kconfig
> >>> @@ -145,6 +145,10 @@ config CLPS711X_IRQCHIP
> >>> select SPARSE_IRQ
> >>> default y
> >>>
> >>> +config OMPIC
> >>> + bool
> >>> + select IRQ_DOMAIN
> >>
> >> Why do you need to select IRQ_DOMAIN? This driver doesn't seem to use any...
> >
> > Right, I will look to remove that.
> >
> >>> +
> >>> config OR1K_PIC
> >>> bool
> >>> select IRQ_DOMAIN
> >>> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> >>> index e88d856cc09c..123047d7a20d 100644
> >>> --- a/drivers/irqchip/Makefile
> >>> +++ b/drivers/irqchip/Makefile
> >>> @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
> >>> obj-$(CONFIG_METAG) += irq-metag-ext.o
> >>> obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
> >>> obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
> >>> +obj-$(CONFIG_OMPIC) += irq-ompic.o
> >>> obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
> >>> obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
> >>> obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
> >>> diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
> >>> new file mode 100644
> >>> index 000000000000..438819f8a5a7
> >>> --- /dev/null
> >>> +++ b/drivers/irqchip/irq-ompic.c
> >>> @@ -0,0 +1,117 @@
> >>> +/*
> >>> + * Open Multi-Processor Interrupt Controller driver
> >>> + *
> >>> + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >>> + *
> >>> + * This file is licensed under the terms of the GNU General Public License
> >>> + * version 2. This program is licensed "as is" without any warranty of any
> >>> + * kind, whether express or implied.
> >>> + */
> >>> +
> >>> +#include <linux/io.h>
> >>> +#include <linux/interrupt.h>
> >>> +#include <linux/smp.h>
> >>> +#include <linux/of.h>
> >>> +#include <linux/of_irq.h>
> >>> +#include <linux/of_address.h>
> >>> +#include <linux/irqchip/chained_irq.h>
> >>
> >> Don't think you need this.
> >>
> >>> +#include <linux/delay.h>
> >>
> >> Nor this.
> >
> > OK on both.
> >
> >>> +
> >>> +#include <linux/irqchip.h>
> >>> +
> >>> +#define OMPIC_IPI_BASE 0x0
> >>> +#define OMPIC_IPI_CTRL(cpu) (OMPIC_IPI_BASE + 0x0 + (cpu)*8)
> >>> +#define OMPIC_IPI_STAT(cpu) (OMPIC_IPI_BASE + 0x4 + (cpu)*8)
> >>
> >> In the DT binding you say that "size can be arbitrary based on the
> >> number of cores the controller has been configured to handle, typically
> >> 8 bytes per core". Here, this is 8 bytes, always, which is not exactly
> >> the same. What is the architectural value, if any? If there is none,
> >> then the per-core size should either come from DT or some other mean
> >> (register?).
> >
> > I mean the address space is 8 bytes x number-of-cores. Thats what I meant
> > by arbitrary, I guess its better for me to be explicit. There is no
> > register that we can check to confirm the configuration of ompic. But I
> > guess we can check the CPU NUMCORES register and compare it to the DT
> > address space to do a sanity check.
>
> Thanks for the explanation. So the code is OK, but the DT should be more
> rigorous in saying that there is 8 bytes per CPU. And yes to the check
> if that can be done at this stage.
I will update that.
> >
> >>> +
> >>> +#define OMPIC_IPI_CTRL_IRQ_ACK (1 << 31)
> >>> +#define OMPIC_IPI_CTRL_IRQ_GEN (1 << 30)
> >>> +#define OMPIC_IPI_CTRL_DST(cpu) (((cpu) & 0x3fff) << 16)
> >>> +
> >>> +#define OMPIC_IPI_STAT_IRQ_PENDING (1 << 30)
> >>> +
> >>> +#define OMPIC_IPI_DATA(x) ((x) & 0xffff)
> >>> +
> >>> +static struct {
> >>> + unsigned long ops;
> >>> +} ipi_data[NR_CPUS];
> >>
> >> In general, a per cpu data structure is better expressed as a percpu
> >> data structure (yes, I'm in a funny mood this morning). Otherwise,
> >> you're going to thrash more than just the receiver and the sender, but
> >> also all the other CPUs that have their data in the same cache line.
> >
> > Right, that makes sense, I am not sure why that was done this way. I think
> > I borrowed from alpha which has the extra __cacheline_aligned annotations.
> > I forgot to come back and fix this. Ill do as you suggest, thank you.
> >
> > Excerpt from alpha:
> >
> > static struct {
> > unsigned long bits ____cacheline_aligned;
> > } ipi_data[NR_CPUS] __cacheline_aligned;
>
> Yup, __cacheline_aligned is key here, as it will have the same effect as
> the percpu stuff from that point of view.
Right, I think in this case I rather use the percpu API rather then
depending on how well our compiler implements the __cacheline_aligned
annotations.
> >>> +
> >>> +static void __iomem *ompic_base;
> >>> +
> >>> +static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
> >>> +{
> >>> + return ioread32be(base + offset);
> >>> +}
> >>> +
> >>> +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
> >>> +{
> >>> + iowrite32be(data, base + offset);
> >>> +}
> >>> +
> >>> +#ifdef CONFIG_SMP
> >>
> >> This code is only selected when CONFIG_SMP=y.
> >
> > Yes, that is right, as below:
> >
> > set_smp_cross_call(ompic_raise_softirq);
> >
> > The set_smp_cross_call() function from smp.c is only defined for smp. Do
> > you think thats wrong or needed extra comments? This is similar to other
> > chips in irqchip/ for archs which use set_smp_cross_call().
>
> Other irqchips can often be compiled for both SMP and !SMP, hence the
> need of a #ifdef. In your case, this driver is only compiled when SMP is
> selected, so you're pretty much guaranteed that this symbol is available.
Right, I'll remove it.
> >
> >>> +void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)
> >>> +{
> >>
> >> What is "irq" here? How is it guaranteed to fit in an unsigned long?
> >
> > Here irq is the `enum ipi_msg_type` which is guaranteed to fit in unsigned
> > long. Porbably its better to rename as msg or ipi_msg?
>
> You should certainly make sure your "enum ipi_msg_type" is capped at the
> number of bits of unsigned long. And yes to ipi_msg, which is a better
> name than irq. Also, you could change the types of ompic_raise_softirq
> and set_smp_cross_call, so that you use the enum instead of an int here.
OK.
I had a go at changing the type to the enum, but I realize that would
require moving the enum definition into our asm/smp.h which I rather not do
at the moment for sake of keeping it private inside of smp.c. This follows
what other architectures do as well.
> >
> >>> + unsigned int dst_cpu;
> >>> + unsigned int src_cpu = smp_processor_id();
> >>> +
> >>> + for_each_cpu(dst_cpu, mask) {
> >>> + set_bit(irq, &ipi_data[dst_cpu].ops);
> >>> +
> >>> + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
> >>> + OMPIC_IPI_CTRL_IRQ_GEN |
> >>> + OMPIC_IPI_CTRL_DST(dst_cpu) |
> >>> + OMPIC_IPI_DATA(1));
> >>
> >> What guarantees that the action of set_bit can be observed by the target
> >> CPU? set-bit gives you atomicity, but no barrier.
> >
> > The bit will not be read by target CPUs until after the ompic_writereg()
> > which will trigger the target CPU interrupt to be raised. OpenRISC stores
> > are ordered.
>
> Are they really ordered irrespective of the memory type (one is
> cacheable RAM, the other is a device...)?
>
> And assuming they are (which I find a bit odd), that doesn't necessarily
> guarantee that the interrupt will only be delivered once the effect of
> set_bit can be seen on the target CPU...
OpenRISC might be a bit odd here, but I think this is correct. On OpenRISC
the atomic instructions also imply a pipeline flush for stores and loads
(l.swa/l.lwa). This is highlighted in the architecture spec section 7.3 [0].
[0] https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
-Stafford
> > This will work on OpenRISC, but should I be thinking of other architectures
> > as well for all drivers? Or do you think this will be an issue on
> > OpenRISC?
>
> I definitely think this could be an issue with OpenRISC, but only
> someone familiar with the OpenRISC architecture can say whether I'm
> right or wrong. I'm just guessing at the moment.
>
> [...]
>
> > Thank you for the feedback, I will clean this up and resubmit with the
> > comments on the other thread.
> >
> > In terms of commit path, do you think its ok for this to go in via the
> > OpenRISC arch path?
>
> Sure, that's fine by me.
>
> M.
> --
> Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 05/13] irqchip: add initial support for ompic
2017-09-03 22:12 ` Stafford Horne
@ 2017-09-04 7:35 ` Marc Zyngier
0 siblings, 0 replies; 34+ messages in thread
From: Marc Zyngier @ 2017-09-04 7:35 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Openrisc, Stefan Kristiansson, Thomas Gleixner,
Jason Cooper, Rob Herring, Mark Rutland, Jonas Bonn, devicetree
On 03/09/17 23:12, Stafford Horne wrote:
> On Fri, Sep 01, 2017 at 06:25:01PM +0100, Marc Zyngier wrote:
>> On 01/09/17 02:24, Stafford Horne wrote:
>>> On Thu, Aug 31, 2017 at 10:28:01AM +0100, Marc Zyngier wrote:
>>>> On 30/08/17 22:58, Stafford Horne wrote:
>>>>> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[...]
>>>>> + unsigned int dst_cpu;
>>>>> + unsigned int src_cpu = smp_processor_id();
>>>>> +
>>>>> + for_each_cpu(dst_cpu, mask) {
>>>>> + set_bit(irq, &ipi_data[dst_cpu].ops);
>>>>> +
>>>>> + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
>>>>> + OMPIC_IPI_CTRL_IRQ_GEN |
>>>>> + OMPIC_IPI_CTRL_DST(dst_cpu) |
>>>>> + OMPIC_IPI_DATA(1));
>>>>
>>>> What guarantees that the action of set_bit can be observed by the target
>>>> CPU? set-bit gives you atomicity, but no barrier.
>>>
>>> The bit will not be read by target CPUs until after the ompic_writereg()
>>> which will trigger the target CPU interrupt to be raised. OpenRISC stores
>>> are ordered.
>>
>> Are they really ordered irrespective of the memory type (one is
>> cacheable RAM, the other is a device...)?
>>
>> And assuming they are (which I find a bit odd), that doesn't necessarily
>> guarantee that the interrupt will only be delivered once the effect of
>> set_bit can be seen on the target CPU...
>
> OpenRISC might be a bit odd here, but I think this is correct. On OpenRISC
> the atomic instructions also imply a pipeline flush for stores and loads
> (l.swa/l.lwa). This is highlighted in the architecture spec section 7.3 [0].
OK, fair enough. This is quite unusual (and I'm prepared to bet that
this will be relaxed in future evolutions of the architecture), but
that's indeed the gospel.
Please add a comment between set_bit and writereg so that we know we've
been through this discussion already.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 05/13] irqchip: add initial support for ompic
2017-08-30 21:58 ` [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne
2017-08-31 9:28 ` Marc Zyngier
@ 2017-08-31 10:59 ` Mark Rutland
2017-09-01 13:59 ` Stafford Horne
1 sibling, 1 reply; 34+ messages in thread
From: Mark Rutland @ 2017-08-31 10:59 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Openrisc, Stefan Kristiansson, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Jonas Bonn, devicetree
On Thu, Aug 31, 2017 at 06:58:36AM +0900, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> IPI driver for OpenRISC Multicore programmable interrupt controller as
> described in the Multicore support section of the OpenRISC 1.2
> proposed architecture specification:
>
> https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing. This IPI device is the
> only external device required for enabling SMP on OpenRISC.
I'm a little confused. Is this device the whole "ompic", a sub-device
thereof, or an independent IP block connected to it?
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> .../bindings/interrupt-controller/ompic.txt | 22 ++++
> arch/openrisc/Kconfig | 1 +
> drivers/irqchip/Kconfig | 4 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++
> 5 files changed, 145 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> create mode 100644 drivers/irqchip/irq-ompic.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> new file mode 100644
> index 000000000000..4176ecc3366d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> @@ -0,0 +1,22 @@
> +OpenRISC Multicore Programmable Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : This should be "ompic"
This needs a vendor prefix.
Presumably, this should be "opencores,ompic"? (pending whether this is
actually the whole ompic, as above).
> +- reg : Specifies base physical address and size of the register space. The
> + size can be arbitrary based on the number of cores the controller has
> + been configured to handle, typically 8 bytes per core.
How are those regions correlated with CPUs?
e.g. is there a fixed relationship with a physical CPU id, or some
mechanism by which the relationship can be probed dynamically?
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- #interrupt-cells : Specifies the number of cells needed to encode an
> + interrupt source. The value shall be 1.
No flags? Does this not need edge/level configuration or active high/low
configuration?
> +- interrupts : Specifies the interrupt line to which the ompic is wired.
What is this interrupt used for?
Is this some percpu interrupt used to proxy the IPI? It feels very odd
to assume such a thing from the parent irqchip. Surely this is
intimately coupled with that?
> +
> +Example:
> +
> +ompic: ompic {
> + compatible = "ompic";
> + reg = <0x98000000 16>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupts = <1>;
> +};
[...]
> +static struct {
> + unsigned long ops;
> +} ipi_data[NR_CPUS];
> +
> +static void __iomem *ompic_base;
Is there guaranteed to only be one of these system-wide?
[...]
> +void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)
> +{
> + unsigned int dst_cpu;
> + unsigned int src_cpu = smp_processor_id();
> +
> + for_each_cpu(dst_cpu, mask) {
> + set_bit(irq, &ipi_data[dst_cpu].ops);
> +
> + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
> + OMPIC_IPI_CTRL_IRQ_GEN |
> + OMPIC_IPI_CTRL_DST(dst_cpu) |
> + OMPIC_IPI_DATA(1));
> + }
Here you assume that the mapping is big enough to cover these registers,
but the ompic_of_init() function didn't sanity-check the size, so this
is not guaranteed.
[...]
> +int __init ompic_of_init(struct device_node *node, struct device_node *parent)
> +{
> + int irq;
> +
> + if (WARN_ON(!node))
> + return -ENODEV;
Given this function is only invoked if the kernel found a node with a
matching compatible string, how can this possibly happen?
> + memset(ipi_data, 0, sizeof(ipi_data));
As ipi_data was static, it is already zeroed.
> +
> + ompic_base = of_iomap(node, 0);
What if this failed?
> +
> + irq = irq_of_parse_and_map(node, 0);
What if this is missing?
> + setup_irq(irq, &ompi_ipi_irqaction);
As covered earlier, I;m confused by this. I'd expect that your root
irqchip would handle the IPIs, and hence need to probe nothing from the
DT for those.
Here we're assuming the IRQ is wired up to some per-cpu interrupt that
we can treat as an IPI, and that the parent irqchip handles that
appropriately, which seems very odd.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 05/13] irqchip: add initial support for ompic
2017-08-31 10:59 ` Mark Rutland
@ 2017-09-01 13:59 ` Stafford Horne
0 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-09-01 13:59 UTC (permalink / raw)
To: Mark Rutland
Cc: LKML, Openrisc, Stefan Kristiansson, Thomas Gleixner,
Jason Cooper, Marc Zyngier, Rob Herring, Jonas Bonn, devicetree
On Thu, Aug 31, 2017 at 11:59:40AM +0100, Mark Rutland wrote:
> On Thu, Aug 31, 2017 at 06:58:36AM +0900, Stafford Horne wrote:
> > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >
> > IPI driver for OpenRISC Multicore programmable interrupt controller as
> > described in the Multicore support section of the OpenRISC 1.2
> > proposed architecture specification:
> >
> > https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
> >
> > Each OpenRISC core contains a full interrupt controller which is used in
> > the SMP architecture for interrupt balancing. This IPI device is the
> > only external device required for enabling SMP on OpenRISC.
>
> I'm a little confused. Is this device the whole "ompic", a sub-device
> thereof, or an independent IP block connected to it?
This device *is* the ompic, it currently just handles IPI communication,
but was originally thought it should do more, i.e. distribute device
interrupts, hence the name. For now, the ompic device only handles IPI.
Perhaps we can change the name? If you think that's needed I can discuss
with Stefan (the creator).
This is documented in the pdf, but here is an ascii diagram to help.
Notes
o The ompic generates a level interrupt to the CPU PIC when a message is
ready. Messages are delivered via the memory bus.
o The ompic does not have any interrupt input lines.
o The ompic must be wired to the same irq line on each core.
o Devices must be wired to the same irq line on each core.
o This seems strange, but in the end very little extra hardware is needed
to enable smp.
+---------+ +---------+
| CPU | | CPU |
| Core 0 |<==\ (memory access) /==>| Core 1 |
| [ PIC ]| | | | [ PIC ]|
+----^-^--+ | | +----^-^--+
| | v v | |
<====|=|=================================|=|==> (memory bus)
| | ^ ^ | |
(ipi | +------|---------+--------|-------|-+ (device irq)
irq | | | | |
core0)| +------|---------|--------|-------+ (ipi irq core1)
| | | | |
+----o-o-+ | +--------+ |
| ompic |<===/ | Device |<===/
| IPI | +--------+
+--------+
> > Pending ops are stored in a memory bit mask which can allow multiple
> > pending operations to be set and serviced at a time. This is mostly
> > borrowed from the alpha IPI implementation.
> >
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> > .../bindings/interrupt-controller/ompic.txt | 22 ++++
> > arch/openrisc/Kconfig | 1 +
> > drivers/irqchip/Kconfig | 4 +
> > drivers/irqchip/Makefile | 1 +
> > drivers/irqchip/irq-ompic.c | 117 +++++++++++++++++++++
> > 5 files changed, 145 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> > create mode 100644 drivers/irqchip/irq-ompic.c
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> > new file mode 100644
> > index 000000000000..4176ecc3366d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/ompic.txt
> > @@ -0,0 +1,22 @@
> > +OpenRISC Multicore Programmable Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible : This should be "ompic"
>
> This needs a vendor prefix.
>
> Presumably, this should be "opencores,ompic"? (pending whether this is
> actually the whole ompic, as above).
As discussed above this is the ompic.
In terms of vendor, this and further openrisc development is no longer
associated with opencores, that company just hosts the old opencores.org
website but is not assisting in openrisc development any longer. Perhaps
"openrisc,ompic" or "openrisc,ipi".
This also I would like to get final say from Stefan, but any suggestions
are welcome.
> > +- reg : Specifies base physical address and size of the register space. The
> > + size can be arbitrary based on the number of cores the controller has
> > + been configured to handle, typically 8 bytes per core.
>
> How are those regions correlated with CPUs?
>
> e.g. is there a fixed relationship with a physical CPU id, or some
> mechanism by which the relationship can be probed dynamically?
There should only be one region.
core id 0 is associated with registers at address 0x0 and 0x4
core id 1 is associated with registers at address 0x8 and 0xc
etc.
This is can't be probed. Should this be documented here? That seems more
of something that is internal to the driver. I think the only thing some
one would want to set in TD is the register space size which should be be 8
x number-of-cores.
> > +- interrupt-controller : Identifies the node as an interrupt controller
> > +- #interrupt-cells : Specifies the number of cells needed to encode an
> > + interrupt source. The value shall be 1.
>
> No flags? Does this not need edge/level configuration or active high/low
> configuration?
No flags, this maybe I am confused on, the ompic does not receive any
interrupts. The input to the ompic are register writes which raise/clear
interrupts on the target CPUs. So maybe it should not define an
'interrupt-controller' or '#interrupt-cells' tag. But then should it be an
irqchip? Since its facilitates the IPI I think this is the right place.
> > +- interrupts : Specifies the interrupt line to which the ompic is wired.
>
> What is this interrupt used for?
>
> Is this some percpu interrupt used to proxy the IPI? It feels very odd
> to assume such a thing from the parent irqchip. Surely this is
> intimately coupled with that?
This represents which IRQ line on each cpu the IPI is connected to (it must
be connected to the same IRQ line on each CPU.
i.e.
interrupt-parent = <&pic>;
> > +
> > +Example:
> > +
> > +ompic: ompic {
> > + compatible = "ompic";
> > + reg = <0x98000000 16>;
> > + #interrupt-cells = <1>;
> > + interrupt-controller;
> > + interrupts = <1>;
> > +};
>
> [...]
>
> > +static struct {
> > + unsigned long ops;
> > +} ipi_data[NR_CPUS];
> > +
> > +static void __iomem *ompic_base;
>
> Is there guaranteed to only be one of these system-wide?
Yes, that should be guaranteed, but I can look for moving this into a per
device structure.
> [...]
>
> > +void ompic_raise_softirq(const struct cpumask *mask, unsigned int irq)
> > +{
> > + unsigned int dst_cpu;
> > + unsigned int src_cpu = smp_processor_id();
> > +
> > + for_each_cpu(dst_cpu, mask) {
> > + set_bit(irq, &ipi_data[dst_cpu].ops);
> > +
> > + ompic_writereg(ompic_base, OMPIC_IPI_CTRL(src_cpu),
> > + OMPIC_IPI_CTRL_IRQ_GEN |
> > + OMPIC_IPI_CTRL_DST(dst_cpu) |
> > + OMPIC_IPI_DATA(1));
> > + }
>
> Here you assume that the mapping is big enough to cover these registers,
> but the ompic_of_init() function didn't sanity-check the size, so this
> is not guaranteed.
OK, I will add some sanity checking.
> [...]
>
> > +int __init ompic_of_init(struct device_node *node, struct device_node *parent)
> > +{
> > + int irq;
> > +
> > + if (WARN_ON(!node))
> > + return -ENODEV;
>
> Given this function is only invoked if the kernel found a node with a
> matching compatible string, how can this possibly happen?
Right, I think now. Will fix.
> > + memset(ipi_data, 0, sizeof(ipi_data));
>
> As ipi_data was static, it is already zeroed.
Right, will fix.
> > +
> > + ompic_base = of_iomap(node, 0);
>
> What if this failed?
Right will fix.
> > +
> > + irq = irq_of_parse_and_map(node, 0);
>
> What if this is missing?
OK, I will do some error checking.
>
> > + setup_irq(irq, &ompi_ipi_irqaction);
>
> As covered earlier, I;m confused by this. I'd expect that your root
> irqchip would handle the IPIs, and hence need to probe nothing from the
> DT for those.
>
> Here we're assuming the IRQ is wired up to some per-cpu interrupt that
> we can treat as an IPI, and that the parent irqchip handles that
> appropriately, which seems very odd.
I hope the comments above help to clarify this. By appropriately you mean
level/edge active high/low? The ompic and openrisc internal pic have been
designed to be compatible.
Thanks for the review. Between this and the comments from Marc I have a
bit of work to do. Please let me know if you have any further questions.
-Stafford
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 06/13] openrisc: initial SMP support
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (4 preceding siblings ...)
2017-08-30 21:58 ` [PATCH 05/13] irqchip: add initial support for ompic Stafford Horne
@ 2017-08-30 21:58 ` Stafford Horne
2017-08-30 22:02 ` [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
` (6 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 21:58 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stefan Kristiansson, Stafford Horne, Jonas Bonn,
Kirill A. Shutemov, Jan Henrik Weinstock, Sebastian Macke,
Andrew Morton, Doug Ledford, Bart Van Assche, Alexander Duyck,
Masahiro Yamada, Olof Kindgren, Rob Herring, Thomas Gleixner,
Paul Gortmaker, Ingo Molnar
From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
This patch introduces the SMP support for the OpenRISC architecture.
The SMP architecture requires cores which have multicore features which
have been introduced a few years back including:
- New SPRS SPR_COREID SPR_NUMCORES
- Shadow SPRs
- Atomic Instructions
- Cache Coherency
- A wired in IPI controller
This patch adds all of the SMP specific changes to core infrastructure,
it looks big but it needs to go all together as its hard to split this
one up.
Boot loader spinning of second cpu is not supported yet, it's assumed
that Linux is booted straight after cpu reset.
The bulk of these changes are trivial changes to refactor to use per cpu
data structures throughout. The addition of the smp.c and changes in
time.c are the changes. Some specific notes:
MM changes
----------
The reason why this is created as an array, and not with DEFINE_PER_CPU
is that doing it this way, we'll save a load in the tlb-miss handler
(the load from __per_cpu_offset).
TLB Flush
---------
The SMP implementation of flush_tlb_* works by sending out a
function-call IPI to all the non-local cpus by using the generic
on_each_cpu() function.
Currently, all flush_tlb_* functions will result in a flush_tlb_all(),
which has always been the behaviour in the UP case.
CPU INFO
--------
This creates a per cpu cpuinfo struct and fills it out accordingly for
each activated cpu. show_cpuinfo is also updated to reflect new version
information in later versions of the spec.
SMP API
-------
This imitates the arm64 implementation by having a smp_cross_call
callback that can be set by set_smp_cross_call to initiate an IPI and a
handle_IPI function that is expected to be called from an IPI irqchip
driver.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: added cpu stop, checkpatch fixes, wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 17 ++-
arch/openrisc/include/asm/cpuinfo.h | 5 +-
arch/openrisc/include/asm/mmu_context.h | 2 +-
arch/openrisc/include/asm/pgtable.h | 2 +-
arch/openrisc/include/asm/serial.h | 2 +-
arch/openrisc/include/asm/smp.h | 26 ++++
arch/openrisc/include/asm/spr_defs.h | 14 ++
arch/openrisc/include/asm/tlbflush.h | 25 +++-
arch/openrisc/kernel/Makefile | 1 +
arch/openrisc/kernel/dma.c | 14 +-
arch/openrisc/kernel/head.S | 97 ++++++++++++-
arch/openrisc/kernel/setup.c | 155 +++++++++++++--------
arch/openrisc/kernel/smp.c | 234 ++++++++++++++++++++++++++++++++
arch/openrisc/kernel/time.c | 51 ++++---
arch/openrisc/lib/delay.c | 2 +-
arch/openrisc/mm/fault.c | 4 +-
arch/openrisc/mm/init.c | 2 +-
arch/openrisc/mm/tlb.c | 16 +--
18 files changed, 560 insertions(+), 109 deletions(-)
create mode 100644 arch/openrisc/include/asm/smp.h
create mode 100644 arch/openrisc/kernel/smp.c
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index dd7e55e7e42d..b59e2ef84534 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -21,8 +21,10 @@ config OPENRISC
select HAVE_UID16
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
+ select GENERIC_CLOCKEVENTS_BROADCAST
select GENERIC_STRNCPY_FROM_USER
select GENERIC_STRNLEN_USER
+ select GENERIC_SMP_IDLE_THREAD
select MODULES_USE_ELF_RELA
select HAVE_DEBUG_STACKOVERFLOW
select OR1K_PIC
@@ -107,8 +109,19 @@ config OPENRISC_HAVE_INST_DIV
endmenu
config NR_CPUS
- int
- default "1"
+ int "Maximum number of CPUs (2-32)"
+ range 2 32
+ depends on SMP
+ default "2"
+
+config SMP
+ bool "Symmetric Multi-Processing support"
+ help
+ This enables support for systems with more than one CPU. If you have
+ a system with only one CPU, say N. If you have a system with more
+ than one CPU, say Y.
+
+ If you don't know what to do here, say N.
source kernel/Kconfig.hz
source kernel/Kconfig.preempt
diff --git a/arch/openrisc/include/asm/cpuinfo.h b/arch/openrisc/include/asm/cpuinfo.h
index ec10679d6429..1bcf29072973 100644
--- a/arch/openrisc/include/asm/cpuinfo.h
+++ b/arch/openrisc/include/asm/cpuinfo.h
@@ -19,7 +19,7 @@
#ifndef __ASM_OPENRISC_CPUINFO_H
#define __ASM_OPENRISC_CPUINFO_H
-struct cpuinfo {
+struct cpuinfo_or1k {
u32 clock_frequency;
u32 icache_size;
@@ -31,6 +31,7 @@ struct cpuinfo {
u32 dcache_ways;
};
-extern struct cpuinfo cpuinfo;
+extern struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
+extern void setup_cpuinfo(void);
#endif /* __ASM_OPENRISC_CPUINFO_H */
diff --git a/arch/openrisc/include/asm/mmu_context.h b/arch/openrisc/include/asm/mmu_context.h
index e94b814d2e3c..c380d8caf84f 100644
--- a/arch/openrisc/include/asm/mmu_context.h
+++ b/arch/openrisc/include/asm/mmu_context.h
@@ -34,7 +34,7 @@ extern void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* registers like cr3 on the i386
*/
-extern volatile pgd_t *current_pgd; /* defined in arch/openrisc/mm/fault.c */
+extern volatile pgd_t *current_pgd[]; /* defined in arch/openrisc/mm/fault.c */
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
index ff97374ca069..47eae2f78d2d 100644
--- a/arch/openrisc/include/asm/pgtable.h
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -94,7 +94,7 @@ extern void paging_init(void);
* 64 MB of vmalloc area is comparable to what's available on other arches.
*/
-#define VMALLOC_START (PAGE_OFFSET-0x04000000)
+#define VMALLOC_START (PAGE_OFFSET-0x04000000UL)
#define VMALLOC_END (PAGE_OFFSET)
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
diff --git a/arch/openrisc/include/asm/serial.h b/arch/openrisc/include/asm/serial.h
index 270a45241639..cb5932f5447a 100644
--- a/arch/openrisc/include/asm/serial.h
+++ b/arch/openrisc/include/asm/serial.h
@@ -29,7 +29,7 @@
* it needs to be correct to get the early console working.
*/
-#define BASE_BAUD (cpuinfo.clock_frequency/16)
+#define BASE_BAUD (cpuinfo_or1k[smp_processor_id()].clock_frequency/16)
#endif /* __KERNEL__ */
diff --git a/arch/openrisc/include/asm/smp.h b/arch/openrisc/include/asm/smp.h
new file mode 100644
index 000000000000..d25ca0952f52
--- /dev/null
+++ b/arch/openrisc/include/asm/smp.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_SMP_H
+#define __ASM_OPENRISC_SMP_H
+
+#include <asm/spr.h>
+#include <asm/spr_defs.h>
+
+#define raw_smp_processor_id() (current_thread_info()->cpu)
+#define hard_smp_processor_id() mfspr(SPR_COREID)
+
+extern void smp_init_cpus(void);
+
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+
+extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
+extern void handle_IPI(int ipinr);
+
+#endif /* __ASM_OPENRISC_SMP_H */
diff --git a/arch/openrisc/include/asm/spr_defs.h b/arch/openrisc/include/asm/spr_defs.h
index 367dac70326a..154b5a1ee579 100644
--- a/arch/openrisc/include/asm/spr_defs.h
+++ b/arch/openrisc/include/asm/spr_defs.h
@@ -51,6 +51,11 @@
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_VR2 (SPRGROUP_SYS + 9)
+#define SPR_AVR (SPRGROUP_SYS + 10)
+#define SPR_EVBAR (SPRGROUP_SYS + 11)
+#define SPR_AECR (SPRGROUP_SYS + 12)
+#define SPR_AESR (SPRGROUP_SYS + 13)
#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
@@ -61,6 +66,8 @@
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
+#define SPR_COREID (SPRGROUP_SYS + 128)
+#define SPR_NUMCORES (SPRGROUP_SYS + 129)
#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
/* Data MMU group */
@@ -135,12 +142,19 @@
#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
#define SPR_VR_RES 0x0000ffc0 /* Reserved */
#define SPR_VR_REV 0x0000003f /* Processor revision */
+#define SPR_VR_UVRP 0x00000040 /* Updated Version Registers Present */
#define SPR_VR_VER_OFF 24
#define SPR_VR_CFG_OFF 16
#define SPR_VR_REV_OFF 0
/*
+ * Bit definitions for the Version Register 2
+ */
+#define SPR_VR2_CPUID 0xff000000 /* Processor ID */
+#define SPR_VR2_VER 0x00ffffff /* Processor version */
+
+/*
* Bit definitions for the Unit Present Register
*
*/
diff --git a/arch/openrisc/include/asm/tlbflush.h b/arch/openrisc/include/asm/tlbflush.h
index 6a2accd6cb67..94227f0eaf6d 100644
--- a/arch/openrisc/include/asm/tlbflush.h
+++ b/arch/openrisc/include/asm/tlbflush.h
@@ -33,13 +33,26 @@
* - flush_tlb_page(vma, vmaddr) flushes one page
* - flush_tlb_range(mm, start, end) flushes a range of pages
*/
+extern void local_flush_tlb_all(void);
+extern void local_flush_tlb_mm(struct mm_struct *mm);
+extern void local_flush_tlb_page(struct vm_area_struct *vma,
+ unsigned long addr);
+extern void local_flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start,
+ unsigned long end);
-void flush_tlb_all(void);
-void flush_tlb_mm(struct mm_struct *mm);
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
-void flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start,
- unsigned long end);
+#ifndef CONFIG_SMP
+#define flush_tlb_all local_flush_tlb_all
+#define flush_tlb_mm local_flush_tlb_mm
+#define flush_tlb_page local_flush_tlb_page
+#define flush_tlb_range local_flush_tlb_range
+#else
+extern void flush_tlb_all(void);
+extern void flush_tlb_mm(struct mm_struct *mm);
+extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
+extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+ unsigned long end);
+#endif
static inline void flush_tlb(void)
{
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index ec6d9d37cefd..7d94643c878d 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -8,6 +8,7 @@ obj-y := setup.o or32_ksyms.o process.o dma.o \
traps.o time.o irq.o entry.o ptrace.o signal.o \
sys_call_table.o
+obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_OF) += prom.o
diff --git a/arch/openrisc/kernel/dma.c b/arch/openrisc/kernel/dma.c
index b10369b7e31b..a945f00011b4 100644
--- a/arch/openrisc/kernel/dma.c
+++ b/arch/openrisc/kernel/dma.c
@@ -32,6 +32,7 @@ page_set_nocache(pte_t *pte, unsigned long addr,
unsigned long next, struct mm_walk *walk)
{
unsigned long cl;
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
pte_val(*pte) |= _PAGE_CI;
@@ -42,7 +43,7 @@ page_set_nocache(pte_t *pte, unsigned long addr,
flush_tlb_page(NULL, addr);
/* Flush page out of dcache */
- for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo.dcache_block_size)
+ for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
mtspr(SPR_DCBFR, cl);
return 0;
@@ -140,6 +141,7 @@ or1k_map_page(struct device *dev, struct page *page,
{
unsigned long cl;
dma_addr_t addr = page_to_phys(page) + offset;
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
return addr;
@@ -148,13 +150,13 @@ or1k_map_page(struct device *dev, struct page *page,
case DMA_TO_DEVICE:
/* Flush the dcache for the requested range */
for (cl = addr; cl < addr + size;
- cl += cpuinfo.dcache_block_size)
+ cl += cpuinfo->dcache_block_size)
mtspr(SPR_DCBFR, cl);
break;
case DMA_FROM_DEVICE:
/* Invalidate the dcache for the requested range */
for (cl = addr; cl < addr + size;
- cl += cpuinfo.dcache_block_size)
+ cl += cpuinfo->dcache_block_size)
mtspr(SPR_DCBIR, cl);
break;
default:
@@ -213,9 +215,10 @@ or1k_sync_single_for_cpu(struct device *dev,
{
unsigned long cl;
dma_addr_t addr = dma_handle;
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
/* Invalidate the dcache for the requested range */
- for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
+ for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)
mtspr(SPR_DCBIR, cl);
}
@@ -226,9 +229,10 @@ or1k_sync_single_for_device(struct device *dev,
{
unsigned long cl;
dma_addr_t addr = dma_handle;
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
/* Flush the dcache for the requested range */
- for (cl = addr; cl < addr + size; cl += cpuinfo.dcache_block_size)
+ for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)
mtspr(SPR_DCBFR, cl);
}
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1e49895408f4..a9972dc103f8 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -158,12 +158,38 @@
/* =========================================================[ macros ]=== */
-
+#ifdef CONFIG_SMP
#define GET_CURRENT_PGD(reg,t1) \
LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
+ l.mfspr t1,r0,SPR_COREID ;\
+ l.slli t1,t1,2 ;\
+ l.add reg,reg,t1 ;\
tophys (t1,reg) ;\
l.lwz reg,0(t1)
+#else
+#define GET_CURRENT_PGD(reg,t1) \
+ LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
+ tophys (t1,reg) ;\
+ l.lwz reg,0(t1)
+#endif
+/* Load r10 from current_thread_info_set - clobbers r1 and r30 */
+#ifdef CONFIG_SMP
+#define GET_CURRENT_THREAD_INFO \
+ LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
+ tophys (r30,r1) ;\
+ l.mfspr r10,r0,SPR_COREID ;\
+ l.slli r10,r10,2 ;\
+ l.add r30,r30,r10 ;\
+ /* r10: current_thread_info */ ;\
+ l.lwz r10,0(r30)
+#else
+#define GET_CURRENT_THREAD_INFO \
+ LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
+ tophys (r30,r1) ;\
+ /* r10: current_thread_info */ ;\
+ l.lwz r10,0(r30)
+#endif
/*
* DSCR: this is a common hook for handling exceptions. it will save
@@ -206,10 +232,7 @@
l.bnf 2f /* kernel_mode */ ;\
EXCEPTION_T_STORE_SP /* delay slot */ ;\
1: /* user_mode: */ ;\
- LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
- tophys (r30,r1) ;\
- /* r10: current_thread_info */ ;\
- l.lwz r10,0(r30) ;\
+ GET_CURRENT_THREAD_INFO ;\
tophys (r30,r10) ;\
l.lwz r1,(TI_KSP)(r30) ;\
/* fall through */ ;\
@@ -530,6 +553,12 @@ _start:
CLEAR_GPR(r30)
CLEAR_GPR(r31)
+#ifdef CONFIG_SMP
+ l.mfspr r26,r0,SPR_COREID
+ l.sfeq r26,r0
+ l.bnf secondary_wait
+ l.nop
+#endif
/*
* set up initial ksp and current
*/
@@ -681,6 +710,64 @@ _flush_tlb:
l.jr r9
l.nop
+#ifdef CONFIG_SMP
+secondary_wait:
+ l.mfspr r25,r0,SPR_COREID
+ l.movhi r3,hi(secondary_release)
+ l.ori r3,r3,lo(secondary_release)
+ tophys(r4, r3)
+ l.lwz r3,0(r4)
+ l.sfeq r25,r3
+ l.bnf secondary_wait
+ l.nop
+ /* fall through to secondary_init */
+
+secondary_init:
+ /*
+ * set up initial ksp and current
+ */
+ LOAD_SYMBOL_2_GPR(r10, secondary_thread_info)
+ tophys (r30,r10)
+ l.lwz r10,0(r30)
+ l.addi r1,r10,THREAD_SIZE
+ tophys (r30,r10)
+ l.sw TI_KSP(r30),r1
+
+ l.jal _ic_enable
+ l.nop
+
+ l.jal _dc_enable
+ l.nop
+
+ l.jal _flush_tlb
+ l.nop
+
+ /*
+ * enable dmmu & immu
+ */
+ l.mfspr r30,r0,SPR_SR
+ l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
+ l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
+ l.or r30,r30,r28
+ /*
+ * This is a bit tricky, we need to switch over from physical addresses
+ * to virtual addresses on the fly.
+ * To do that, we first set up ESR with the IME and DME bits set.
+ * Then EPCR is set to secondary_start and then a l.rfe is issued to
+ * "jump" to that.
+ */
+ l.mtspr r0,r30,SPR_ESR_BASE
+ LOAD_SYMBOL_2_GPR(r30, secondary_start)
+ l.mtspr r0,r30,SPR_EPCR_BASE
+ l.rfe
+
+secondary_start:
+ LOAD_SYMBOL_2_GPR(r30, secondary_start_kernel)
+ l.jr r30
+ l.nop
+
+#endif
+
/* ========================================[ cache ]=== */
/* alignment here so we don't change memory offsets with
diff --git a/arch/openrisc/kernel/setup.c b/arch/openrisc/kernel/setup.c
index dbf5ee95a0d5..11c853e73d74 100644
--- a/arch/openrisc/kernel/setup.c
+++ b/arch/openrisc/kernel/setup.c
@@ -93,7 +93,7 @@ static void __init setup_memory(void)
memblock_dump_all();
}
-struct cpuinfo cpuinfo;
+struct cpuinfo_or1k cpuinfo_or1k[NR_CPUS];
static void print_cpuinfo(void)
{
@@ -101,12 +101,13 @@ static void print_cpuinfo(void)
unsigned long vr = mfspr(SPR_VR);
unsigned int version;
unsigned int revision;
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
version = (vr & SPR_VR_VER) >> 24;
revision = (vr & SPR_VR_REV);
printk(KERN_INFO "CPU: OpenRISC-%x (revision %d) @%d MHz\n",
- version, revision, cpuinfo.clock_frequency / 1000000);
+ version, revision, cpuinfo->clock_frequency / 1000000);
if (!(upr & SPR_UPR_UP)) {
printk(KERN_INFO
@@ -117,15 +118,15 @@ static void print_cpuinfo(void)
if (upr & SPR_UPR_DCP)
printk(KERN_INFO
"-- dcache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo.dcache_size, cpuinfo.dcache_block_size,
- cpuinfo.dcache_ways);
+ cpuinfo->dcache_size, cpuinfo->dcache_block_size,
+ cpuinfo->dcache_ways);
else
printk(KERN_INFO "-- dcache disabled\n");
if (upr & SPR_UPR_ICP)
printk(KERN_INFO
"-- icache: %4d bytes total, %2d bytes/line, %d way(s)\n",
- cpuinfo.icache_size, cpuinfo.icache_block_size,
- cpuinfo.icache_ways);
+ cpuinfo->icache_size, cpuinfo->icache_block_size,
+ cpuinfo->icache_ways);
else
printk(KERN_INFO "-- icache disabled\n");
@@ -153,32 +154,50 @@ static void print_cpuinfo(void)
printk(KERN_INFO "-- custom unit(s)\n");
}
+static struct device_node *setup_find_cpu_node(int cpu)
+{
+ u32 hwid;
+ struct device_node *cpun;
+ struct device_node *cpus = of_find_node_by_path("/cpus");
+
+ for_each_available_child_of_node(cpus, cpun) {
+ if (of_property_read_u32(cpun, "reg", &hwid))
+ continue;
+ if (hwid == cpu)
+ return cpun;
+ }
+
+ return NULL;
+}
+
void __init setup_cpuinfo(void)
{
struct device_node *cpu;
unsigned long iccfgr, dccfgr;
unsigned long cache_set_size;
+ int cpu_id = smp_processor_id();
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu_id];
- cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481");
+ cpu = setup_find_cpu_node(cpu_id);
if (!cpu)
- panic("No compatible CPU found in device tree...\n");
+ panic("Couldn't find CPU%d in device tree...\n", cpu_id);
iccfgr = mfspr(SPR_ICCFGR);
- cpuinfo.icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
+ cpuinfo->icache_ways = 1 << (iccfgr & SPR_ICCFGR_NCW);
cache_set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3);
- cpuinfo.icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
- cpuinfo.icache_size =
- cache_set_size * cpuinfo.icache_ways * cpuinfo.icache_block_size;
+ cpuinfo->icache_block_size = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> 7);
+ cpuinfo->icache_size =
+ cache_set_size * cpuinfo->icache_ways * cpuinfo->icache_block_size;
dccfgr = mfspr(SPR_DCCFGR);
- cpuinfo.dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
+ cpuinfo->dcache_ways = 1 << (dccfgr & SPR_DCCFGR_NCW);
cache_set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3);
- cpuinfo.dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
- cpuinfo.dcache_size =
- cache_set_size * cpuinfo.dcache_ways * cpuinfo.dcache_block_size;
+ cpuinfo->dcache_block_size = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> 7);
+ cpuinfo->dcache_size =
+ cache_set_size * cpuinfo->dcache_ways * cpuinfo->dcache_block_size;
if (of_property_read_u32(cpu, "clock-frequency",
- &cpuinfo.clock_frequency)) {
+ &cpuinfo->clock_frequency)) {
printk(KERN_WARNING
"Device tree missing CPU 'clock-frequency' parameter."
"Assuming frequency 25MHZ"
@@ -251,8 +270,8 @@ void __init detect_unit_config(unsigned long upr, unsigned long mask,
void calibrate_delay(void)
{
const int *val;
- struct device_node *cpu = NULL;
- cpu = of_find_compatible_node(NULL, NULL, "opencores,or1200-rtlsvn481");
+ struct device_node *cpu = setup_find_cpu_node(smp_processor_id());
+
val = of_get_property(cpu, "clock-frequency", NULL);
if (!val)
panic("no cpu 'clock-frequency' parameter in device tree");
@@ -268,6 +287,10 @@ void __init setup_arch(char **cmdline_p)
setup_cpuinfo();
+#ifdef CONFIG_SMP
+ smp_init_cpus();
+#endif
+
/* process 1's initial memory region is the kernel code/data */
init_mm.start_code = (unsigned long)_stext;
init_mm.end_code = (unsigned long)_etext;
@@ -302,48 +325,72 @@ void __init setup_arch(char **cmdline_p)
static int show_cpuinfo(struct seq_file *m, void *v)
{
- unsigned long vr;
- int version, revision;
+ unsigned int vr, cpucfgr;
+ unsigned int avr;
+ unsigned int version;
+ unsigned long n = (unsigned long) v - 1;
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[n];
vr = mfspr(SPR_VR);
- version = (vr & SPR_VR_VER) >> 24;
- revision = vr & SPR_VR_REV;
-
- seq_printf(m,
- "cpu\t\t: OpenRISC-%x\n"
- "revision\t: %d\n"
- "frequency\t: %ld\n"
- "dcache size\t: %d bytes\n"
- "dcache block size\t: %d bytes\n"
- "dcache ways\t: %d\n"
- "icache size\t: %d bytes\n"
- "icache block size\t: %d bytes\n"
- "icache ways\t: %d\n"
- "immu\t\t: %d entries, %lu ways\n"
- "dmmu\t\t: %d entries, %lu ways\n"
- "bogomips\t: %lu.%02lu\n",
- version,
- revision,
- loops_per_jiffy * HZ,
- cpuinfo.dcache_size,
- cpuinfo.dcache_block_size,
- cpuinfo.dcache_ways,
- cpuinfo.icache_size,
- cpuinfo.icache_block_size,
- cpuinfo.icache_ways,
- 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
- 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW),
- 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
- 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW),
- (loops_per_jiffy * HZ) / 500000,
- ((loops_per_jiffy * HZ) / 5000) % 100);
+ cpucfgr = mfspr(SPR_CPUCFGR);
+
+#ifdef CONFIG_SMP
+ seq_printf(m, "processor\t\t: %ld\n", n);
+#endif
+ if (vr & SPR_VR_UVRP) {
+ vr = mfspr(SPR_VR2);
+ version = vr & SPR_VR2_VER;
+ avr = mfspr(SPR_AVR);
+ seq_printf(m, "cpu architecture\t: "
+ "OpenRISC 1000 (%d.%d-rev%d)\n",
+ (avr >> 24) & 0xff,
+ (avr >> 16) & 0xff,
+ (avr >> 8) & 0xff);
+ seq_printf(m, "cpu implementation id\t: 0x%x\n",
+ (vr & SPR_VR2_CPUID) >> 24);
+ seq_printf(m, "cpu version\t\t: 0x%x\n", version);
+ } else {
+ version = (vr & SPR_VR_VER) >> 24;
+ seq_printf(m, "cpu\t\t\t: OpenRISC-%x\n", version);
+ seq_printf(m, "revision\t\t: %d\n", vr & SPR_VR_REV);
+ }
+ seq_printf(m, "frequency\t\t: %ld\n", loops_per_jiffy * HZ);
+ seq_printf(m, "dcache size\t\t: %d bytes\n", cpuinfo->dcache_size);
+ seq_printf(m, "dcache block size\t: %d bytes\n",
+ cpuinfo->dcache_block_size);
+ seq_printf(m, "dcache ways\t\t: %d\n", cpuinfo->dcache_ways);
+ seq_printf(m, "icache size\t\t: %d bytes\n", cpuinfo->icache_size);
+ seq_printf(m, "icache block size\t: %d bytes\n",
+ cpuinfo->icache_block_size);
+ seq_printf(m, "icache ways\t\t: %d\n", cpuinfo->icache_ways);
+ seq_printf(m, "immu\t\t\t: %d entries, %lu ways\n",
+ 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2),
+ 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW));
+ seq_printf(m, "dmmu\t\t\t: %d entries, %lu ways\n",
+ 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2),
+ 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW));
+ seq_printf(m, "bogomips\t\t: %lu.%02lu\n",
+ (loops_per_jiffy * HZ) / 500000,
+ ((loops_per_jiffy * HZ) / 5000) % 100);
+
+ seq_puts(m, "features\t\t: ");
+ seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB32S ? "orbis32" : "");
+ seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OB64S ? "orbis64" : "");
+ seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF32S ? "orfpx32" : "");
+ seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OF64S ? "orfpx64" : "");
+ seq_printf(m, "%s ", cpucfgr & SPR_CPUCFGR_OV64S ? "orvdx64" : "");
+ seq_puts(m, "\n");
+
+ seq_puts(m, "\n");
+
return 0;
}
static void *c_start(struct seq_file *m, loff_t * pos)
{
- /* We only have one CPU... */
- return *pos < 1 ? (void *)1 : NULL;
+ unsigned long i = *pos;
+
+ return i < NR_CPUS ? (void *) (i + 1) : NULL;
}
static void *c_next(struct seq_file *m, void *v, loff_t * pos)
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
new file mode 100644
index 000000000000..ae93b84062ff
--- /dev/null
+++ b/arch/openrisc/kernel/smp.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * Based on arm64 and arc implementations
+ * Copyright (C) 2013 ARM Ltd.
+ * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/cpu.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <asm/cpuinfo.h>
+#include <asm/mmu_context.h>
+#include <asm/tlbflush.h>
+
+volatile unsigned long secondary_release = -1;
+struct thread_info *secondary_thread_info;
+
+enum ipi_msg_type {
+ IPI_RESCHEDULE,
+ IPI_CALL_FUNC,
+ IPI_CALL_FUNC_SINGLE,
+};
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static int boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ /*
+ * set synchronisation state between this boot processor
+ * and the secondary one
+ */
+ spin_lock(&boot_lock);
+
+ secondary_release = cpu;
+
+ /*
+ * now the secondary core is starting up let it run its
+ * calibrations, then wait for it to finish
+ */
+ spin_unlock(&boot_lock);
+
+ return 0;
+}
+
+void __init smp_prepare_boot_cpu(void)
+{
+}
+
+void __init smp_init_cpus(void)
+{
+ int i;
+
+ for (i = 0; i < NR_CPUS; i++)
+ set_cpu_possible(i, true);
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+ int i;
+
+ /*
+ * Initialise the present map, which describes the set of CPUs
+ * actually populated at the present time.
+ */
+ for (i = 0; i < max_cpus; i++)
+ set_cpu_present(i, true);
+}
+
+void __init smp_cpus_done(unsigned int max_cpus)
+{
+}
+
+static DECLARE_COMPLETION(cpu_running);
+
+int __cpu_up(unsigned int cpu, struct task_struct *idle)
+{
+ int ret;
+
+ secondary_thread_info = task_thread_info(idle);
+ current_pgd[cpu] = init_mm.pgd;
+
+ ret = boot_secondary(cpu, idle);
+ if (ret == 0) {
+ wait_for_completion_timeout(&cpu_running,
+ msecs_to_jiffies(1000));
+ if (!cpu_online(cpu))
+ ret = -EIO;
+ }
+
+ return ret;
+}
+
+extern void openrisc_clockevent_init(void);
+
+asmlinkage __init void secondary_start_kernel(void)
+{
+ struct mm_struct *mm = &init_mm;
+ unsigned int cpu = smp_processor_id();
+ /*
+ * All kernel threads share the same mm context; grab a
+ * reference and switch to it.
+ */
+ atomic_inc(&mm->mm_count);
+ current->active_mm = mm;
+ cpumask_set_cpu(cpu, mm_cpumask(mm));
+
+ pr_info("CPU%u: Booted secondary processor\n", cpu);
+
+ setup_cpuinfo();
+ openrisc_clockevent_init();
+
+ notify_cpu_starting(cpu);
+
+ /*
+ * OK, now it's safe to let the boot CPU continue
+ */
+ set_cpu_online(cpu, true);
+ complete(&cpu_running);
+
+ local_irq_enable();
+
+ /*
+ * OK, it's off to the idle thread for us
+ */
+ cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
+}
+
+void handle_IPI(int ipinr)
+{
+ unsigned int cpu = smp_processor_id();
+
+ switch (ipinr) {
+ case IPI_RESCHEDULE:
+ scheduler_ipi();
+ break;
+
+ case IPI_CALL_FUNC:
+ generic_smp_call_function_interrupt();
+ break;
+
+ case IPI_CALL_FUNC_SINGLE:
+ generic_smp_call_function_single_interrupt();
+ break;
+
+ default:
+ WARN(1, "CPU%u: Unknown IPI message 0x%x\n", cpu, ipinr);
+ break;
+ }
+}
+
+static void (*smp_cross_call)(const struct cpumask *, unsigned int);
+
+void smp_send_reschedule(int cpu)
+{
+ smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
+}
+
+static void stop_this_cpu(void *dummy)
+{
+ /* Remove this CPU */
+ set_cpu_online(smp_processor_id(), false);
+
+ local_irq_disable();
+ /* CPU Doze */
+ if (mfspr(SPR_UPR) & SPR_UPR_PMP)
+ mtspr(SPR_PMR, mfspr(SPR_PMR) | SPR_PMR_DME);
+ /* If that didn't work, infinite loop */
+ while (1)
+ ;
+}
+
+void smp_send_stop(void)
+{
+ smp_call_function(stop_this_cpu, NULL, 0);
+}
+
+/* not supported, yet */
+int setup_profiling_timer(unsigned int multiplier)
+{
+ return -EINVAL;
+}
+
+void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
+{
+ smp_cross_call = fn;
+}
+
+void arch_send_call_function_single_ipi(int cpu)
+{
+ smp_cross_call(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
+}
+
+void arch_send_call_function_ipi_mask(const struct cpumask *mask)
+{
+ smp_cross_call(mask, IPI_CALL_FUNC);
+}
+
+/* TLB flush operations - Performed on each CPU*/
+static inline void ipi_flush_tlb_all(void *ignored)
+{
+ local_flush_tlb_all();
+}
+
+void flush_tlb_all(void)
+{
+ on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+}
+
+/*
+ * FIXME: implement proper functionality instead of flush_tlb_all.
+ * *But*, as things currently stands, the local_tlb_flush_* functions will
+ * all boil down to local_tlb_flush_all anyway.
+ */
+void flush_tlb_mm(struct mm_struct *mm)
+{
+ on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+}
+
+void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+{
+ on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+}
+
+void flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+ on_each_cpu(ipi_flush_tlb_all, NULL, 1);
+}
diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c
index 687c11d048d7..ab04eaedbf8d 100644
--- a/arch/openrisc/kernel/time.c
+++ b/arch/openrisc/kernel/time.c
@@ -53,13 +53,32 @@ static int openrisc_timer_set_next_event(unsigned long delta,
* timers) we cannot enable the PERIODIC feature. The tick timer can run using
* one-shot events, so no problem.
*/
+DEFINE_PER_CPU(struct clock_event_device, clockevent_openrisc_timer);
-static struct clock_event_device clockevent_openrisc_timer = {
- .name = "openrisc_timer_clockevent",
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .rating = 300,
- .set_next_event = openrisc_timer_set_next_event,
-};
+void openrisc_clockevent_init(void)
+{
+ unsigned int cpu = smp_processor_id();
+ struct clock_event_device *evt =
+ &per_cpu(clockevent_openrisc_timer, cpu);
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[cpu];
+
+ mtspr(SPR_TTMR, SPR_TTMR_CR);
+
+#ifdef CONFIG_SMP
+ evt->broadcast = tick_broadcast;
+#endif
+ evt->name = "openrisc_timer_clockevent",
+ evt->features = CLOCK_EVT_FEAT_ONESHOT,
+ evt->rating = 300,
+ evt->set_next_event = openrisc_timer_set_next_event,
+
+ evt->cpumask = cpumask_of(cpu);
+
+ /* We only have 28 bits */
+ clockevents_config_and_register(evt, cpuinfo->clock_frequency,
+ 100, 0x0fffffff);
+
+}
static inline void timer_ack(void)
{
@@ -83,7 +102,9 @@ static inline void timer_ack(void)
irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
- struct clock_event_device *evt = &clockevent_openrisc_timer;
+ unsigned int cpu = smp_processor_id();
+ struct clock_event_device *evt =
+ &per_cpu(clockevent_openrisc_timer, cpu);
timer_ack();
@@ -99,24 +120,12 @@ irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
return IRQ_HANDLED;
}
-static __init void openrisc_clockevent_init(void)
-{
- clockevent_openrisc_timer.cpumask = cpumask_of(0);
-
- /* We only have 28 bits */
- clockevents_config_and_register(&clockevent_openrisc_timer,
- cpuinfo.clock_frequency,
- 100, 0x0fffffff);
-
-}
-
/**
* Clocksource: Based on OpenRISC timer/counter
*
* This sets up the OpenRISC Tick Timer as a clock source. The tick timer
* is 32 bits wide and runs at the CPU clock frequency.
*/
-
static u64 openrisc_timer_read(struct clocksource *cs)
{
return (u64) mfspr(SPR_TTCR);
@@ -132,7 +141,9 @@ static struct clocksource openrisc_timer = {
static int __init openrisc_timer_init(void)
{
- if (clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency))
+ struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
+
+ if (clocksource_register_hz(&openrisc_timer, cpuinfo->clock_frequency))
panic("failed to register clocksource");
/* Enable the incrementer: 'continuous' mode with interrupt disabled */
diff --git a/arch/openrisc/lib/delay.c b/arch/openrisc/lib/delay.c
index 8b13fdf43ec6..a92bd621aa1f 100644
--- a/arch/openrisc/lib/delay.c
+++ b/arch/openrisc/lib/delay.c
@@ -25,7 +25,7 @@
int read_current_timer(unsigned long *timer_value)
{
- *timer_value = mfspr(SPR_TTCR);
+ *timer_value = get_cycles();
return 0;
}
diff --git a/arch/openrisc/mm/fault.c b/arch/openrisc/mm/fault.c
index e310ab499385..d0021dfae20a 100644
--- a/arch/openrisc/mm/fault.c
+++ b/arch/openrisc/mm/fault.c
@@ -33,7 +33,7 @@ unsigned long pte_errors; /* updated by do_page_fault() */
/* __PHX__ :: - check the vmalloc_fault in do_page_fault()
* - also look into include/asm-or32/mmu_context.h
*/
-volatile pgd_t *current_pgd;
+volatile pgd_t *current_pgd[NR_CPUS];
extern void die(char *, struct pt_regs *, long);
@@ -319,7 +319,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long address,
phx_mmu("vmalloc_fault");
*/
- pgd = (pgd_t *)current_pgd + offset;
+ pgd = (pgd_t *)current_pgd[smp_processor_id()] + offset;
pgd_k = init_mm.pgd + offset;
/* Since we're two-level, we don't need to do both
diff --git a/arch/openrisc/mm/init.c b/arch/openrisc/mm/init.c
index f67d82b9d22f..6972d5d6f23f 100644
--- a/arch/openrisc/mm/init.c
+++ b/arch/openrisc/mm/init.c
@@ -147,7 +147,7 @@ void __init paging_init(void)
* (even if it is most probably not used until the next
* switch_mm)
*/
- current_pgd = init_mm.pgd;
+ current_pgd[smp_processor_id()] = init_mm.pgd;
end = (unsigned long)__va(max_low_pfn * PAGE_SIZE);
diff --git a/arch/openrisc/mm/tlb.c b/arch/openrisc/mm/tlb.c
index 683bd4d31c7c..6c253a2e86bc 100644
--- a/arch/openrisc/mm/tlb.c
+++ b/arch/openrisc/mm/tlb.c
@@ -49,7 +49,7 @@
*
*/
-void flush_tlb_all(void)
+void local_flush_tlb_all(void)
{
int i;
unsigned long num_tlb_sets;
@@ -86,7 +86,7 @@ void flush_tlb_all(void)
#define flush_itlb_page_no_eir(addr) \
mtspr_off(SPR_ITLBMR_BASE(0), ITLB_OFFSET(addr), 0);
-void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
+void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
if (have_dtlbeir)
flush_dtlb_page_eir(addr);
@@ -99,8 +99,8 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
flush_itlb_page_no_eir(addr);
}
-void flush_tlb_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end)
+void local_flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
{
int addr;
bool dtlbeir;
@@ -129,13 +129,13 @@ void flush_tlb_range(struct vm_area_struct *vma,
* This should be changed to loop over over mm and call flush_tlb_range.
*/
-void flush_tlb_mm(struct mm_struct *mm)
+void local_flush_tlb_mm(struct mm_struct *mm)
{
/* Was seeing bugs with the mm struct passed to us. Scrapped most of
this function. */
/* Several architctures do this */
- flush_tlb_all();
+ local_flush_tlb_all();
}
/* called in schedule() just before actually doing the switch_to */
@@ -149,14 +149,14 @@ void switch_mm(struct mm_struct *prev, struct mm_struct *next,
* might be invalid at points where we still need to derefer
* the pgd.
*/
- current_pgd = next->pgd;
+ current_pgd[smp_processor_id()] = next->pgd;
/* We don't have context support implemented, so flush all
* entries belonging to previous map
*/
if (prev != next)
- flush_tlb_mm(prev);
+ local_flush_tlb_mm(prev);
}
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (5 preceding siblings ...)
2017-08-30 21:58 ` [PATCH 06/13] openrisc: initial SMP support Stafford Horne
@ 2017-08-30 22:02 ` Stafford Horne
2017-08-30 22:02 ` [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
` (5 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 22:02 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson,
Jan Henrik Weinstock
During SMP testing we were getting the below warning after booting the
secondary cpu:
[ 0.060000] BUG: scheduling while atomic: swapper/1/0/0x00000000
This change follows similar patterns from other architectures to start
the schduler with preempt disabled.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/include/asm/thread_info.h | 2 +-
arch/openrisc/kernel/smp.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/openrisc/include/asm/thread_info.h b/arch/openrisc/include/asm/thread_info.h
index 6e619a79a401..c229aa6bb502 100644
--- a/arch/openrisc/include/asm/thread_info.h
+++ b/arch/openrisc/include/asm/thread_info.h
@@ -74,7 +74,7 @@ struct thread_info {
.task = &tsk, \
.flags = 0, \
.cpu = 0, \
- .preempt_count = 1, \
+ .preempt_count = INIT_PREEMPT_COUNT, \
.addr_limit = KERNEL_DS, \
.ksp = 0, \
}
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index ae93b84062ff..24f7aa45b0ba 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -125,6 +125,7 @@ asmlinkage __init void secondary_start_kernel(void)
local_irq_enable();
+ preempt_disable();
/*
* OK, it's off to the idle thread for us
*/
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 08/13] openrisc: sleep instead of spin on secondary wait
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (6 preceding siblings ...)
2017-08-30 22:02 ` [PATCH 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
@ 2017-08-30 22:02 ` Stafford Horne
2017-08-30 22:02 ` [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
` (4 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 22:02 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson,
Masahiro Yamada, Andrew Morton, Jan Henrik Weinstock
Currently we do a spin on secondary cpus when waiting to boot. This causes
issues with power consumption as well as qemu cycle burning (it starves
cpu 0 from actually being able to boot.)
The secondary interrupt handler is stored in the init section so as to
allow it to be reclaimed after boot. However, if we ever want to
support hotplug this may need to change.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/kernel/head.S | 44 ++++++++++++++++++++++++++++++++++++++++++--
arch/openrisc/kernel/smp.c | 9 +++++++--
2 files changed, 49 insertions(+), 4 deletions(-)
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index a9972dc103f8..ea065e091bd5 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -712,9 +712,37 @@ _flush_tlb:
#ifdef CONFIG_SMP
secondary_wait:
+ /* Doze the cpu until we are asked to run */
+ /* Setup special secondary exception handler */
+ LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
+ tophys(r25,r3)
+ l.mtspr r0,r25,SPR_EVBAR
+
+ /* Enable Interrupts */
+ l.mfspr r25,r0,SPR_SR
+ l.ori r25,r25,SPR_SR_IEE
+ l.mtspr r0,r25,SPR_SR
+
+ /* Unmask interrupts interrupts */
+ l.mfspr r25,r0,SPR_PICMR
+ l.ori r25,r25,0xffff
+ l.mtspr r0,r25,SPR_PICMR
+
+ /* Doze */
+ l.mfspr r25,r0,SPR_PMR
+ LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
+ l.or r25,r25,r3
+ l.mtspr r0,r25,SPR_PMR
+
+ /* Wakeup - Restore exception handler */
+ l.mtspr r0,r0,SPR_EVBAR
+
+ /*
+ * Check if we actually got the wake signal, if not go-back to
+ * sleep.
+ */
l.mfspr r25,r0,SPR_COREID
- l.movhi r3,hi(secondary_release)
- l.ori r3,r3,lo(secondary_release)
+ LOAD_SYMBOL_2_GPR(r3, secondary_release)
tophys(r4, r3)
l.lwz r3,0(r4)
l.sfeq r25,r3
@@ -1663,6 +1691,18 @@ ENTRY(_early_uart_init)
l.jr r9
l.nop
+ .section .init.text, "ax"
+ .align 0x1000
+ .global _secondary_evbar
+_secondary_evbar:
+
+ .space 0x800
+ /* Just disable interrupts and Return */
+ l.ori r3,r0,SPR_SR_SM
+ l.mtspr r0,r3,SPR_ESR_BASE
+ l.rfe
+
+
.section .rodata
_string_unhandled_exception:
.string "\n\rRunarunaround: Unhandled exception 0x\0"
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 24f7aa45b0ba..7696f9274608 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -18,10 +18,13 @@
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
+static void (*smp_cross_call)(const struct cpumask *, unsigned int);
+
volatile unsigned long secondary_release = -1;
struct thread_info *secondary_thread_info;
enum ipi_msg_type {
+ IPI_WAKEUP,
IPI_RESCHEDULE,
IPI_CALL_FUNC,
IPI_CALL_FUNC_SINGLE,
@@ -38,6 +41,7 @@ static int boot_secondary(unsigned int cpu, struct task_struct *idle)
spin_lock(&boot_lock);
secondary_release = cpu;
+ smp_cross_call(cpumask_of(cpu), IPI_WAKEUP);
/*
* now the secondary core is starting up let it run its
@@ -137,6 +141,9 @@ void handle_IPI(int ipinr)
unsigned int cpu = smp_processor_id();
switch (ipinr) {
+ case IPI_WAKEUP:
+ break;
+
case IPI_RESCHEDULE:
scheduler_ipi();
break;
@@ -155,8 +162,6 @@ void handle_IPI(int ipinr)
}
}
-static void (*smp_cross_call)(const struct cpumask *, unsigned int);
-
void smp_send_reschedule(int cpu)
{
smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (7 preceding siblings ...)
2017-08-30 22:02 ` [PATCH 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
@ 2017-08-30 22:02 ` Stafford Horne
2017-08-30 22:03 ` [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
` (3 subsequent siblings)
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 22:02 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Jan Henrik Weinstock, Stafford Horne, Jonas Bonn,
Stefan Kristiansson, Peter Zijlstra (Intel), Masahiro Yamada,
Masami Hiramatsu, Al Viro, Luis R. Rodriguez, Nicolas Dichtel,
Michal Hocko, Kirill A. Shutemov
From: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
On OpenRISC the icache does not snoop data stores. This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory. It supports both
SMP and UP flushing.
This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.
Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 11 ++++
arch/openrisc/include/asm/Kbuild | 1 -
arch/openrisc/include/asm/cacheflush.h | 96 ++++++++++++++++++++++++++++++++++
arch/openrisc/include/asm/pgtable.h | 16 +++---
arch/openrisc/kernel/smp.c | 15 ++++++
arch/openrisc/mm/Makefile | 2 +-
arch/openrisc/mm/cache.c | 61 +++++++++++++++++++++
7 files changed, 194 insertions(+), 8 deletions(-)
create mode 100644 arch/openrisc/include/asm/cacheflush.h
create mode 100644 arch/openrisc/mm/cache.c
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index b59e2ef84534..9e01dc6e1c0b 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -77,6 +77,17 @@ config OR1K_1200
endchoice
+config DCACHE_WRITETHROUGH
+ bool "Have write through data caches"
+ default n
+ help
+ Select this if your implementation features write through data caches.
+ Selecting 'N' here will allow the kernel to force flushing of data
+ caches at relevant times. Most OpenRISC implementations support write-
+ through data caches.
+
+ If unsure say N here
+
config OPENRISC_BUILTIN_DTB
string "Builtin DTB"
default ""
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5f066780d870..6eb16719549e 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,7 +1,6 @@
generic-y += barrier.h
generic-y += bug.h
generic-y += bugs.h
-generic-y += cacheflush.h
generic-y += checksum.h
generic-y += clkdev.h
generic-y += current.h
diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include/asm/cacheflush.h
new file mode 100644
index 000000000000..70f46fd7a074
--- /dev/null
+++ b/arch/openrisc/include/asm/cacheflush.h
@@ -0,0 +1,96 @@
+/*
+ * OpenRISC Linux
+ *
+ * Linux architectural port borrowing liberally from similar works of
+ * others. All original copyrights apply as per the original source
+ * declaration.
+ *
+ * OpenRISC implementation:
+ * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
+ * et al.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_CACHEFLUSH_H
+#define __ASM_CACHEFLUSH_H
+
+#include <linux/mm.h>
+
+/*
+ * Helper function for flushing or invalidating entire pages from data
+ * and instruction caches. SMP needs a little extra work, since we need
+ * to flush the pages on all cpus.
+ */
+extern void local_dcache_page_flush(struct page *page);
+extern void local_icache_page_inv(struct page *page);
+
+/*
+ * Data cache flushing always happen on the local cpu. Instruction cache
+ * invalidations need to be broadcasted to all other cpu in the system in
+ * case of SMP configurations.
+ */
+#ifndef CONFIG_SMP
+#define dcache_page_flush(page) local_dcache_page_flush(page)
+#define icache_page_inv(page) local_icache_page_inv(page)
+#else /* CONFIG_SMP */
+#define dcache_page_flush(page) local_dcache_page_flush(page)
+#define icache_page_inv(page) smp_icache_page_inv(page)
+extern void smp_icache_page_inv(struct page *page);
+#endif /* CONFIG_SMP */
+
+/*
+ * Synchronizes caches. Whenever a cpu writes executable code to memory, this
+ * should be called to make sure the processor sees the newly written code.
+ */
+static inline void sync_icache_dcache(struct page *page)
+{
+ if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
+ dcache_page_flush(page);
+ icache_page_inv(page);
+}
+
+/*
+ * Pages with this bit set need not be flushed/invalidated, since
+ * they have not changed since last flush. New pages start with
+ * PG_arch_1 not set and are therefore dirty by default.
+ */
+#define PG_dc_clean PG_arch_1
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+static inline void flush_dcache_page(struct page *page)
+{
+ clear_bit(PG_dc_clean, &page->flags);
+}
+
+/*
+ * Other interfaces are not required since we do not have virtually
+ * indexed or tagged caches. So we can use the default here.
+ */
+#define flush_cache_all() do { } while (0)
+#define flush_cache_mm(mm) do { } while (0)
+#define flush_cache_dup_mm(mm) do { } while (0)
+#define flush_cache_range(vma, start, end) do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
+#define flush_dcache_mmap_lock(mapping) do { } while (0)
+#define flush_dcache_mmap_unlock(mapping) do { } while (0)
+#define flush_icache_range(start, end) do { } while (0)
+#define flush_icache_page(vma, pg) do { } while (0)
+#define flush_icache_user_range(vma, pg, adr, len) do { } while (0)
+#define flush_cache_vmap(start, end) do { } while (0)
+#define flush_cache_vunmap(start, end) do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+ do { \
+ memcpy(dst, src, len); \
+ if (vma->vm_flags & VM_EXEC) \
+ sync_icache_dcache(page); \
+ } while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+ memcpy(dst, src, len)
+
+#endif /* __ASM_CACHEFLUSH_H */
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
index 47eae2f78d2d..471821e4e810 100644
--- a/arch/openrisc/include/asm/pgtable.h
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -414,15 +414,19 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
-/*
- * or32 doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- *
- * Actually I am not sure on what this could be used for.
- */
+static inline void update_tlb(struct vm_area_struct *vma,
+ unsigned long address, pte_t *pte)
+{
+}
+
+extern void update_cache(struct vm_area_struct *vma,
+ unsigned long address, pte_t *pte);
+
static inline void update_mmu_cache(struct vm_area_struct *vma,
unsigned long address, pte_t *pte)
{
+ update_tlb(vma, address, pte);
+ update_cache(vma, address, pte);
}
/* __PHX__ FIXME, SWAP, this probably doesn't work */
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 7696f9274608..b349d6cb498f 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -17,6 +17,7 @@
#include <asm/cpuinfo.h>
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
static void (*smp_cross_call)(const struct cpumask *, unsigned int);
@@ -238,3 +239,17 @@ void flush_tlb_range(struct vm_area_struct *vma,
{
on_each_cpu(ipi_flush_tlb_all, NULL, 1);
}
+
+/* Instruction cache invalidate - performed on each cpu */
+static void ipi_icache_page_inv(void *arg)
+{
+ struct page *page = arg;
+
+ local_icache_page_inv(page);
+}
+
+void smp_icache_page_inv(struct page *page)
+{
+ on_each_cpu(ipi_icache_page_inv, page, 1);
+}
+EXPORT_SYMBOL(smp_icache_page_inv);
diff --git a/arch/openrisc/mm/Makefile b/arch/openrisc/mm/Makefile
index 324ba2634529..a31b2a42e966 100644
--- a/arch/openrisc/mm/Makefile
+++ b/arch/openrisc/mm/Makefile
@@ -2,4 +2,4 @@
# Makefile for the linux openrisc-specific parts of the memory manager.
#
-obj-y := fault.o tlb.o init.o ioremap.o
+obj-y := fault.o cache.o tlb.o init.o ioremap.o
diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
new file mode 100644
index 000000000000..b747bf1fc1b6
--- /dev/null
+++ b/arch/openrisc/mm/cache.c
@@ -0,0 +1,61 @@
+/*
+ * OpenRISC cache.c
+ *
+ * Linux architectural port borrowing liberally from similar works of
+ * others. All original copyrights apply as per the original source
+ * declaration.
+ *
+ * Modifications for the OpenRISC architecture:
+ * Copyright (C) 2015 Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/spr.h>
+#include <asm/spr_defs.h>
+#include <asm/cache.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+static void cache_loop(struct page *page, const unsigned int reg)
+{
+ unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
+ unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
+
+ while (line < paddr + PAGE_SIZE) {
+ mtspr(reg, line);
+ line += L1_CACHE_BYTES;
+ }
+}
+
+void local_dcache_page_flush(struct page *page)
+{
+ cache_loop(page, SPR_DCBFR);
+}
+EXPORT_SYMBOL(local_dcache_page_flush);
+
+void local_icache_page_inv(struct page *page)
+{
+ cache_loop(page, SPR_ICBIR);
+}
+EXPORT_SYMBOL(local_icache_page_inv);
+
+void update_cache(struct vm_area_struct *vma, unsigned long address,
+ pte_t *pte)
+{
+ unsigned long pfn = pte_val(*pte) >> PAGE_SHIFT;
+ struct page *page = pfn_to_page(pfn);
+ int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
+
+ /*
+ * Since icaches do not snoop for updated data on OpenRISC, we
+ * must write back and invalidate any dirty pages manually. We
+ * can skip data pages, since they will not end up in icaches.
+ */
+ if ((vma->vm_flags & VM_EXEC) && dirty)
+ sync_icache_dcache(page);
+}
+
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (8 preceding siblings ...)
2017-08-30 22:02 ` [PATCH 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
@ 2017-08-30 22:03 ` Stafford Horne
2017-08-31 10:41 ` Mark Rutland
2017-09-11 22:37 ` Pavel Machek
2017-08-30 22:03 ` [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
` (2 subsequent siblings)
12 siblings, 2 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 22:03 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stefan Kristiansson, Stafford Horne, Rob Herring,
Mark Rutland, Jonas Bonn, Krzysztof Kozlowski, devicetree
From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP. This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.
Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++
arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
2 files changed, 124 insertions(+)
create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
create mode 100644 arch/openrisc/configs/simple_smp_defconfig
diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
new file mode 100644
index 000000000000..47c54101baae
--- /dev/null
+++ b/arch/openrisc/boot/dts/simple_smp.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+/ {
+ compatible = "opencores,or1ksim";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&pic>;
+
+ chosen {
+ bootargs = "console=uart,mmio,0x90000000,115200";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x02000000>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "opencores,or1200-rtlsvn481";
+ reg = <0>;
+ clock-frequency = <20000000>;
+ };
+ cpu@1 {
+ compatible = "opencores,or1200-rtlsvn481";
+ reg = <1>;
+ clock-frequency = <20000000>;
+ };
+ };
+
+ ompic: ompic {
+ compatible = "ompic";
+ reg = <0x98000000 16>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <1>;
+ };
+
+ /*
+ * OR1K PIC is built into CPU and accessed via special purpose
+ * registers. It is not addressable and, hence, has no 'reg'
+ * property.
+ */
+ pic: pic {
+ compatible = "opencores,or1k-pic-level";
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+
+ serial0: serial@90000000 {
+ compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
+ reg = <0x90000000 0x100>;
+ interrupts = <2>;
+ clock-frequency = <20000000>;
+ };
+
+};
diff --git a/arch/openrisc/configs/simple_smp_defconfig b/arch/openrisc/configs/simple_smp_defconfig
new file mode 100644
index 000000000000..b6e3c7e158e7
--- /dev/null
+++ b/arch/openrisc/configs/simple_smp_defconfig
@@ -0,0 +1,66 @@
+CONFIG_CROSS_COMPILE="or1k-linux-"
+CONFIG_LOCALVERSION="-simple-smp"
+CONFIG_NO_HZ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_EPOLL is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLOB=y
+CONFIG_MODULES=y
+# CONFIG_BLOCK is not set
+CONFIG_OPENRISC_BUILTIN_DTB="simple_smp"
+CONFIG_SMP=y
+CONFIG_HZ_100=y
+CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CUBIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_NETDEVICES=y
+CONFIG_ETHOC=y
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_XZ_DEC=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_RCU_TRACE is not set
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
2017-08-30 22:03 ` [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
@ 2017-08-31 10:41 ` Mark Rutland
2017-08-31 13:05 ` Stafford Horne
2017-09-11 22:37 ` Pavel Machek
1 sibling, 1 reply; 34+ messages in thread
From: Mark Rutland @ 2017-08-31 10:41 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Openrisc, Stefan Kristiansson, Rob Herring, Jonas Bonn,
Krzysztof Kozlowski, devicetree
On Thu, Aug 31, 2017 at 07:03:11AM +0900, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> Simple enough to be compatible with simulation environments,
> such as verilated systems, QEMU and other targets supporting OpenRISC
> SMP. This also supports our base FPGA SoC's if the cpu frequency is
> upped to 50Mhz.
>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: Added defconfig]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++
> arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
> 2 files changed, 124 insertions(+)
> create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
> create mode 100644 arch/openrisc/configs/simple_smp_defconfig
>
> diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
> new file mode 100644
> index 000000000000..47c54101baae
> --- /dev/null
> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> @@ -0,0 +1,58 @@
> +/dts-v1/;
> +/ {
> + compatible = "opencores,or1ksim";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&pic>;
> +
> + chosen {
> + bootargs = "console=uart,mmio,0x90000000,115200";
> + };
Any reason this isn't using stdout-path?
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x00000000 0x02000000>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu@0 {
> + compatible = "opencores,or1200-rtlsvn481";
> + reg = <0>;
> + clock-frequency = <20000000>;
> + };
> + cpu@1 {
> + compatible = "opencores,or1200-rtlsvn481";
> + reg = <1>;
> + clock-frequency = <20000000>;
> + };
> + };
No enable-method or similar?
Is your SMP bringup/teardown architected?
> +
> + ompic: ompic {
> + compatible = "ompic";
This needs a vendor prefix.
Thanks,
Mark.
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
2017-08-31 10:41 ` Mark Rutland
@ 2017-08-31 13:05 ` Stafford Horne
0 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-31 13:05 UTC (permalink / raw)
To: Mark Rutland
Cc: LKML, Openrisc, Stefan Kristiansson, Rob Herring, Jonas Bonn,
Krzysztof Kozlowski, devicetree
On Thu, Aug 31, 2017 at 11:41:10AM +0100, Mark Rutland wrote:
> On Thu, Aug 31, 2017 at 07:03:11AM +0900, Stafford Horne wrote:
> > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >
> > Simple enough to be compatible with simulation environments,
> > such as verilated systems, QEMU and other targets supporting OpenRISC
> > SMP. This also supports our base FPGA SoC's if the cpu frequency is
> > upped to 50Mhz.
> >
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > [shorne@gmail.com: Added defconfig]
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> > arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++
> > arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
> > 2 files changed, 124 insertions(+)
> > create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
> > create mode 100644 arch/openrisc/configs/simple_smp_defconfig
> >
> > diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
> > new file mode 100644
> > index 000000000000..47c54101baae
> > --- /dev/null
> > +++ b/arch/openrisc/boot/dts/simple_smp.dts
> > @@ -0,0 +1,58 @@
> > +/dts-v1/;
> > +/ {
> > + compatible = "opencores,or1ksim";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + interrupt-parent = <&pic>;
> > +
> > + chosen {
> > + bootargs = "console=uart,mmio,0x90000000,115200";
> > + };
>
> Any reason this isn't using stdout-path?
I didn't know about stdout-path. I will add it.
> > +
> > + memory@0 {
> > + device_type = "memory";
> > + reg = <0x00000000 0x02000000>;
> > + };
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + cpu@0 {
> > + compatible = "opencores,or1200-rtlsvn481";
> > + reg = <0>;
> > + clock-frequency = <20000000>;
> > + };
> > + cpu@1 {
> > + compatible = "opencores,or1200-rtlsvn481";
> > + reg = <1>;
> > + clock-frequency = <20000000>;
> > + };
> > + };
>
> No enable-method or similar?
>
> Is your SMP bringup/teardown architected?
There is no configurable enable-method yet. The current SMP bringup method
is described in the architecture manual (SMP still under review). If you
have any pointers that would be great. See section 10.4
https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
In brief, Currently for SMP bringup both CPU's are expected to reset
directly to the startup vectors. The main CPU (coreid == 0) will start
initialization where the secondary cpu's either spin or sleep until
signalled by the main CPU.
Original patch had cpu's spinning, but after [8/13] secondary cpus will go
into Doze mode.
>
> > +
> > + ompic: ompic {
> > + compatible = "ompic";
>
> This needs a vendor prefix.
This has also been brought up on [5/13], the question of vendor was
anticipated and I discussed with Stefan before sending the patch.
OpenRISC is not part of opencores any longer and this ompic was definitely
not implemented with an existing vendor in mind.
Perhaps we can just call it openrisc,ompic. I will comment more on the
other thread.
Thanks for the review.
-Stafford
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
2017-08-30 22:03 ` [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-08-31 10:41 ` Mark Rutland
@ 2017-09-11 22:37 ` Pavel Machek
2017-09-11 22:55 ` Stafford Horne
1 sibling, 1 reply; 34+ messages in thread
From: Pavel Machek @ 2017-09-11 22:37 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Openrisc, Stefan Kristiansson, Rob Herring, Mark Rutland,
Jonas Bonn, Krzysztof Kozlowski, devicetree
[-- Attachment #1: Type: text/plain, Size: 1437 bytes --]
On Thu 2017-08-31 07:03:11, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> Simple enough to be compatible with simulation environments,
> such as verilated systems, QEMU and other targets supporting OpenRISC
> SMP. This also supports our base FPGA SoC's if the cpu frequency is
> upped to 50Mhz.
>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: Added defconfig]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> arch/openrisc/boot/dts/simple_smp.dts | 58 ++++++++++++++++++++++++++
> arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
> 2 files changed, 124 insertions(+)
> create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
> create mode 100644 arch/openrisc/configs/simple_smp_defconfig
>
> diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
> new file mode 100644
> index 000000000000..47c54101baae
> --- /dev/null
> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> @@ -0,0 +1,58 @@
> +/dts-v1/;
> +/ {
> + compatible = "opencores,or1ksim";
You may want to add some comment on top, explaining what this
is... and perhaps link to some page documenting how to set up
qemu/FPGAs?
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
2017-09-11 22:37 ` Pavel Machek
@ 2017-09-11 22:55 ` Stafford Horne
2017-09-12 7:47 ` Pavel Machek
0 siblings, 1 reply; 34+ messages in thread
From: Stafford Horne @ 2017-09-11 22:55 UTC (permalink / raw)
To: Pavel Machek
Cc: LKML, Openrisc, Stefan Kristiansson, Rob Herring, Mark Rutland,
Jonas Bonn, Krzysztof Kozlowski, devicetree
On Tue, Sep 12, 2017 at 7:37 AM, Pavel Machek <pavel@ucw.cz> wrote:
> On Thu 2017-08-31 07:03:11, Stafford Horne wrote:
>> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>>
[...]
>> +++ b/arch/openrisc/boot/dts/simple_smp.dts
>> @@ -0,0 +1,58 @@
>> +/dts-v1/;
>> +/ {
>> + compatible = "opencores,or1ksim";
>
> You may want to add some comment on top, explaining what this
> is... and perhaps link to some page documenting how to set up
> qemu/FPGAs?
Sure, I can create an entry in Documentation/devicetree/binding
documenting this since its been there for a while but was never properly
documented.
But, just to be clear, what do you mean by page? Are you suggesting
linking to a web page? Or do you mean something in Documentation/...?
-Stafford
^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
2017-09-11 22:55 ` Stafford Horne
@ 2017-09-12 7:47 ` Pavel Machek
2017-09-12 22:15 ` Stafford Horne
0 siblings, 1 reply; 34+ messages in thread
From: Pavel Machek @ 2017-09-12 7:47 UTC (permalink / raw)
To: Stafford Horne
Cc: LKML, Openrisc, Stefan Kristiansson, Rob Herring, Mark Rutland,
Jonas Bonn, Krzysztof Kozlowski, devicetree
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On Tue 2017-09-12 07:55:18, Stafford Horne wrote:
> On Tue, Sep 12, 2017 at 7:37 AM, Pavel Machek <pavel@ucw.cz> wrote:
> > On Thu 2017-08-31 07:03:11, Stafford Horne wrote:
> >> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >>
> [...]
> >> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> >> @@ -0,0 +1,58 @@
> >> +/dts-v1/;
> >> +/ {
> >> + compatible = "opencores,or1ksim";
> >
> > You may want to add some comment on top, explaining what this
> > is... and perhaps link to some page documenting how to set up
> > qemu/FPGAs?
>
> Sure, I can create an entry in Documentation/devicetree/binding
> documenting this since its been there for a while but was never properly
> documented.
Yep, Documentation/devicetree should be mandatory.
> But, just to be clear, what do you mean by page? Are you suggesting
> linking to a web page? Or do you mean something in Documentation/...?
Whatever works for you. Maybe Documentation/ would be better...
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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^ permalink raw reply [flat|nested] 34+ messages in thread* Re: [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators
2017-09-12 7:47 ` Pavel Machek
@ 2017-09-12 22:15 ` Stafford Horne
0 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-09-12 22:15 UTC (permalink / raw)
To: Pavel Machek
Cc: LKML, Openrisc, Stefan Kristiansson, Rob Herring, Mark Rutland,
Jonas Bonn, Krzysztof Kozlowski, devicetree
On Tue, Sep 12, 2017 at 09:47:02AM +0200, Pavel Machek wrote:
> On Tue 2017-09-12 07:55:18, Stafford Horne wrote:
> > On Tue, Sep 12, 2017 at 7:37 AM, Pavel Machek <pavel@ucw.cz> wrote:
> > > On Thu 2017-08-31 07:03:11, Stafford Horne wrote:
> > >> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > >>
> > [...]
> > >> +++ b/arch/openrisc/boot/dts/simple_smp.dts
> > >> @@ -0,0 +1,58 @@
> > >> +/dts-v1/;
> > >> +/ {
> > >> + compatible = "opencores,or1ksim";
> > >
> > > You may want to add some comment on top, explaining what this
> > > is... and perhaps link to some page documenting how to set up
> > > qemu/FPGAs?
> >
> > Sure, I can create an entry in Documentation/devicetree/binding
> > documenting this since its been there for a while but was never properly
> > documented.
>
> Yep, Documentation/devicetree should be mandatory.
>
> > But, just to be clear, what do you mean by page? Are you suggesting
> > linking to a web page? Or do you mean something in Documentation/...?
>
> Whatever works for you. Maybe Documentation/ would be better...
Actually, I forgot, we have something but its here:
arch/openrisc/README.openrisc
I'll work on some patches to move that to Documentation/ and clean it up.
-Stafford
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (9 preceding siblings ...)
2017-08-30 22:03 ` [PATCH 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
@ 2017-08-30 22:03 ` Stafford Horne
2017-08-30 22:03 ` [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-08-30 22:03 ` [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 22:03 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson,
Ingo Molnar, Paul Gortmaker
For lockdep support a reliable stack trace mechanism is needed. This
patch adds support in OpenRISC for the stacktrace framework, implemented
by a simple unwinder api. The unwinder api supports both framepointer
and basic stack tracing.
The unwinder is now used to replace the stack_dump() implementation as
well. The new traces are inline with other architectures trace format:
Call trace:
[<c0004448>] show_stack+0x3c/0x58
[<c031c940>] dump_stack+0xa8/0xe4
[<c0008104>] __cpu_up+0x64/0x130
[<c000d268>] bringup_cpu+0x3c/0x178
[<c000d038>] cpuhp_invoke_callback+0xa8/0x1fc
[<c000d680>] cpuhp_up_callbacks+0x44/0x14c
[<c000e400>] cpu_up+0x14c/0x1bc
[<c041da60>] smp_init+0x104/0x15c
[<c033843c>] ? kernel_init+0x0/0x140
[<c0415e04>] kernel_init_freeable+0xbc/0x25c
[<c033843c>] ? kernel_init+0x0/0x140
[<c0338458>] kernel_init+0x1c/0x140
[<c003a174>] ? schedule_tail+0x18/0xa0
[<c0006b80>] ret_from_fork+0x1c/0x9c
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 4 ++
arch/openrisc/include/asm/unwinder.h | 20 +++++++
arch/openrisc/kernel/Makefile | 3 +-
arch/openrisc/kernel/stacktrace.c | 86 ++++++++++++++++++++++++++++
arch/openrisc/kernel/traps.c | 54 +++---------------
arch/openrisc/kernel/unwinder.c | 105 +++++++++++++++++++++++++++++++++++
6 files changed, 224 insertions(+), 48 deletions(-)
create mode 100644 arch/openrisc/include/asm/unwinder.h
create mode 100644 arch/openrisc/kernel/stacktrace.c
create mode 100644 arch/openrisc/kernel/unwinder.c
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 9e01dc6e1c0b..862b642d380b 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -33,6 +33,7 @@ config OPENRISC
select ARCH_USE_QUEUED_SPINLOCKS
select ARCH_USE_QUEUED_RWLOCKS
select OMPIC if SMP
+ select ARCH_WANT_FRAME_POINTERS
config CPU_BIG_ENDIAN
def_bool y
@@ -60,6 +61,9 @@ config TRACE_IRQFLAGS_SUPPORT
config GENERIC_CSUM
def_bool y
+config STACKTRACE_SUPPORT
+ def_bool y
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/include/asm/unwinder.h b/arch/openrisc/include/asm/unwinder.h
new file mode 100644
index 000000000000..165ec6f02ab8
--- /dev/null
+++ b/arch/openrisc/include/asm/unwinder.h
@@ -0,0 +1,20 @@
+/*
+ * OpenRISC unwinder.h
+ *
+ * Architecture API for unwinding stacks.
+ *
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_UNWINDER_H
+#define __ASM_OPENRISC_UNWINDER_H
+
+void unwind_stack(void *data, unsigned long *stack,
+ void (*trace)(void *data, unsigned long addr,
+ int reliable));
+
+#endif /* __ASM_OPENRISC_UNWINDER_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 7d94643c878d..b4b51a07016a 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -6,9 +6,10 @@ extra-y := head.o vmlinux.lds
obj-y := setup.o or32_ksyms.o process.o dma.o \
traps.o time.o irq.o entry.o ptrace.o signal.o \
- sys_call_table.o
+ sys_call_table.o unwinder.o
obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_OF) += prom.o
diff --git a/arch/openrisc/kernel/stacktrace.c b/arch/openrisc/kernel/stacktrace.c
new file mode 100644
index 000000000000..43f140a28bc7
--- /dev/null
+++ b/arch/openrisc/kernel/stacktrace.c
@@ -0,0 +1,86 @@
+/*
+ * Stack trace utility for OpenRISC
+ *
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Losely based on work from sh and powerpc.
+ */
+
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/sched/debug.h>
+#include <linux/stacktrace.h>
+
+#include <asm/processor.h>
+#include <asm/unwinder.h>
+
+/*
+ * Save stack-backtrace addresses into a stack_trace buffer.
+ */
+static void
+save_stack_address(void *data, unsigned long addr, int reliable)
+{
+ struct stack_trace *trace = data;
+
+ if (!reliable)
+ return;
+
+ if (trace->skip > 0) {
+ trace->skip--;
+ return;
+ }
+
+ if (trace->nr_entries < trace->max_entries)
+ trace->entries[trace->nr_entries++] = addr;
+}
+
+void save_stack_trace(struct stack_trace *trace)
+{
+ unwind_stack(trace, (unsigned long *) &trace, save_stack_address);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
+
+static void
+save_stack_address_nosched(void *data, unsigned long addr, int reliable)
+{
+ struct stack_trace *trace = (struct stack_trace *)data;
+
+ if (!reliable)
+ return;
+
+ if (in_sched_functions(addr))
+ return;
+
+ if (trace->skip > 0) {
+ trace->skip--;
+ return;
+ }
+
+ if (trace->nr_entries < trace->max_entries)
+ trace->entries[trace->nr_entries++] = addr;
+}
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+ unsigned long *sp = NULL;
+
+ if (tsk == current)
+ sp = (unsigned long *) &sp;
+ else
+ sp = (unsigned long *) KSTK_ESP(tsk);
+
+ unwind_stack(trace, sp, save_stack_address_nosched);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
+
+void
+save_stack_trace_regs(struct pt_regs *regs, struct stack_trace *trace)
+{
+ unwind_stack(trace, (unsigned long *) regs->sp,
+ save_stack_address_nosched);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace_regs);
diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c
index 803e9e756f77..4085d72fa5ae 100644
--- a/arch/openrisc/kernel/traps.c
+++ b/arch/openrisc/kernel/traps.c
@@ -38,6 +38,7 @@
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/pgtable.h>
+#include <asm/unwinder.h>
extern char _etext, _stext;
@@ -45,61 +46,20 @@ int kstack_depth_to_print = 0x180;
int lwa_flag;
unsigned long __user *lwa_addr;
-static inline int valid_stack_ptr(struct thread_info *tinfo, void *p)
+void print_trace(void *data, unsigned long addr, int reliable)
{
- return p > (void *)tinfo && p < (void *)tinfo + THREAD_SIZE - 3;
-}
-
-void show_trace(struct task_struct *task, unsigned long *stack)
-{
- struct thread_info *context;
- unsigned long addr;
-
- context = (struct thread_info *)
- ((unsigned long)stack & (~(THREAD_SIZE - 1)));
-
- while (valid_stack_ptr(context, stack)) {
- addr = *stack++;
- if (__kernel_text_address(addr)) {
- printk(" [<%08lx>]", addr);
- print_symbol(" %s", addr);
- printk("\n");
- }
- }
- printk(" =======================\n");
+ pr_emerg("[<%p>] %s%pS\n", (void *) addr, reliable ? "" : "? ",
+ (void *) addr);
}
/* displays a short stack trace */
void show_stack(struct task_struct *task, unsigned long *esp)
{
- unsigned long addr, *stack;
- int i;
-
if (esp == NULL)
esp = (unsigned long *)&esp;
- stack = esp;
-
- printk("Stack dump [0x%08lx]:\n", (unsigned long)esp);
- for (i = 0; i < kstack_depth_to_print; i++) {
- if (kstack_end(stack))
- break;
- if (__get_user(addr, stack)) {
- /* This message matches "failing address" marked
- s390 in ksymoops, so lines containing it will
- not be filtered out by ksymoops. */
- printk("Failing address 0x%lx\n", (unsigned long)stack);
- break;
- }
- stack++;
-
- printk("sp + %02d: 0x%08lx\n", i * 4, addr);
- }
- printk("\n");
-
- show_trace(task, esp);
-
- return;
+ pr_emerg("Call trace:\n");
+ unwind_stack(NULL, esp, print_trace);
}
void show_trace_task(struct task_struct *tsk)
@@ -115,7 +75,7 @@ void show_registers(struct pt_regs *regs)
int in_kernel = 1;
unsigned long esp;
- esp = (unsigned long)(®s->sp);
+ esp = (unsigned long)(regs->sp);
if (user_mode(regs))
in_kernel = 0;
diff --git a/arch/openrisc/kernel/unwinder.c b/arch/openrisc/kernel/unwinder.c
new file mode 100644
index 000000000000..8ae15c2c1845
--- /dev/null
+++ b/arch/openrisc/kernel/unwinder.c
@@ -0,0 +1,105 @@
+/*
+ * OpenRISC unwinder.c
+ *
+ * Reusable arch specific api for unwinding stacks.
+ *
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/sched/task_stack.h>
+#include <linux/kernel.h>
+
+#include <asm/unwinder.h>
+
+#ifdef CONFIG_FRAME_POINTER
+struct or1k_frameinfo {
+ unsigned long *fp;
+ unsigned long ra;
+ unsigned long top;
+};
+
+/*
+ * Verify a frameinfo structure. The return address should be a valid text
+ * address. The frame pointer may be null if its the last frame, otherwise
+ * the frame pointer should point to a location in the stack after the the
+ * top of the next frame up.
+ */
+static inline int or1k_frameinfo_valid(struct or1k_frameinfo *frameinfo)
+{
+ return (frameinfo->fp == NULL ||
+ (!kstack_end(frameinfo->fp) &&
+ frameinfo->fp > &frameinfo->top)) &&
+ __kernel_text_address(frameinfo->ra);
+}
+
+/*
+ * Create a stack trace doing scanning which is frame pointer aware. We can
+ * get reliable stack traces by matching the previously found frame
+ * pointer with the top of the stack address every time we find a valid
+ * or1k_frameinfo.
+ *
+ * Ideally the stack parameter will be passed as FP, but it can not be
+ * guaranteed. Therefore we scan each address looking for the first sign
+ * of a return address.
+ *
+ * The OpenRISC stack frame looks something like the following. The
+ * location SP is held in r1 and location FP is held in r2 when frame pointers
+ * enabled.
+ *
+ * SP -> (top of stack)
+ * - (callee saved registers)
+ * - (local variables)
+ * FP-8 -> previous FP \
+ * FP-4 -> return address |- or1k_frameinfo
+ * FP -> (previous top of stack) /
+ */
+void unwind_stack(void *data, unsigned long *stack,
+ void (*trace)(void *data, unsigned long addr, int reliable))
+{
+ unsigned long *next_fp = NULL;
+ struct or1k_frameinfo *frameinfo = NULL;
+ int reliable = 0;
+
+ while (!kstack_end(stack)) {
+ frameinfo = container_of(stack,
+ struct or1k_frameinfo,
+ top);
+
+ if (__kernel_text_address(frameinfo->ra)) {
+ if (or1k_frameinfo_valid(frameinfo) &&
+ (next_fp == NULL ||
+ next_fp == &frameinfo->top)) {
+ reliable = 1;
+ next_fp = frameinfo->fp;
+ } else
+ reliable = 0;
+
+ trace(data, frameinfo->ra, reliable);
+ }
+ stack++;
+ }
+}
+
+#else /* CONFIG_FRAME_POINTER */
+
+/*
+ * Create a stack trace by doing a simple scan treating all text addresses
+ * as return addresses.
+ */
+void unwind_stack(void *data, unsigned long *stack,
+ void (*trace)(void *data, unsigned long addr, int reliable))
+{
+ unsigned long addr;
+
+ while (!kstack_end(stack)) {
+ addr = *stack++;
+ if (__kernel_text_address(addr))
+ trace(data, addr, 0);
+ }
+}
+#endif /* CONFIG_FRAME_POINTER */
+
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (10 preceding siblings ...)
2017-08-30 22:03 ` [PATCH 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
@ 2017-08-30 22:03 ` Stafford Horne
2017-08-30 22:03 ` [PATCH 13/13] openrisc: add tick timer multicore sync logic Stafford Horne
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 22:03 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson,
Andrew Morton, Masahiro Yamada, Geert Uytterhoeven
Lockdep is needed for proving the spinlocks and rwlocks work fine on our
platform. It also requires calling the trace_hardirqs_off() and
trace_hardirqs_on() pair of routines when entering and exiting an
interrupt.
For OpenRISC the interrupt stack frame does not support frame pointers,
so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's
build up a stack frame each time.
There is one necessary small change in _sys_call_handler to move
interrupt enabling later so they can get re-enabled during syscall
restart. This was done to fix lockdep warnings that are now possible due
to this
patch.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/Kconfig | 3 ++
arch/openrisc/kernel/entry.S | 74 ++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 74 insertions(+), 3 deletions(-)
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 862b642d380b..09d287db4f25 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -64,6 +64,9 @@ config GENERIC_CSUM
config STACKTRACE_SUPPORT
def_bool y
+config LOCKDEP_SUPPORT
+ def_bool y
+
source "init/Kconfig"
source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index 1b7160c79646..690d55272ba6 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -42,6 +42,61 @@
/* =========================================================[ macros ]=== */
+#ifdef CONFIG_TRACE_IRQFLAGS
+/*
+ * Trace irq on/off creating a stack frame.
+ */
+#define TRACE_IRQS_OP(trace_op) \
+ l.sw -8(r1),r2 /* store frame pointer */ ;\
+ l.sw -4(r1),r9 /* store return address */ ;\
+ l.addi r2,r1,0 /* move sp to fp */ ;\
+ l.jal trace_op ;\
+ l.addi r1,r1,-8 ;\
+ l.ori r1,r2,0 /* restore sp */ ;\
+ l.lwz r9,-4(r1) /* restore return address */ ;\
+ l.lwz r2,-8(r1) /* restore fp */ ;\
+/*
+ * Trace irq on/off and save registers we need that would otherwise be
+ * clobbered.
+ */
+#define TRACE_IRQS_SAVE(t1,trace_op) \
+ l.sw -12(r1),t1 /* save extra reg */ ;\
+ l.sw -8(r1),r2 /* store frame pointer */ ;\
+ l.sw -4(r1),r9 /* store return address */ ;\
+ l.addi r2,r1,0 /* move sp to fp */ ;\
+ l.jal trace_op ;\
+ l.addi r1,r1,-12 ;\
+ l.ori r1,r2,0 /* restore sp */ ;\
+ l.lwz r9,-4(r1) /* restore return address */ ;\
+ l.lwz r2,-8(r1) /* restore fp */ ;\
+ l.lwz t1,-12(r1) /* restore extra reg */
+
+#define TRACE_IRQS_OFF TRACE_IRQS_OP(trace_hardirqs_off)
+#define TRACE_IRQS_ON TRACE_IRQS_OP(trace_hardirqs_on)
+#define TRACE_IRQS_ON_SYSCALL \
+ TRACE_IRQS_SAVE(r10,trace_hardirqs_on) ;\
+ l.lwz r3,PT_GPR3(r1) ;\
+ l.lwz r4,PT_GPR4(r1) ;\
+ l.lwz r5,PT_GPR5(r1) ;\
+ l.lwz r6,PT_GPR6(r1) ;\
+ l.lwz r7,PT_GPR7(r1) ;\
+ l.lwz r8,PT_GPR8(r1) ;\
+ l.lwz r11,PT_GPR11(r1)
+#define TRACE_IRQS_OFF_ENTRY \
+ l.lwz r5,PT_SR(r1) ;\
+ l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) ;\
+ l.sfeq r5,r0 /* skip trace if irqs were already off */;\
+ l.bf 1f ;\
+ l.nop ;\
+ TRACE_IRQS_SAVE(r4,trace_hardirqs_off) ;\
+1:
+#else
+#define TRACE_IRQS_OFF
+#define TRACE_IRQS_ON
+#define TRACE_IRQS_OFF_ENTRY
+#define TRACE_IRQS_ON_SYSCALL
+#endif
+
/*
* We need to disable interrupts at beginning of RESTORE_ALL
* since interrupt might come in after we've loaded EPC return address
@@ -124,6 +179,7 @@ handler: ;\
/* r30 already save */ ;\
/* l.sw PT_GPR30(r1),r30*/ ;\
l.sw PT_GPR31(r1),r31 ;\
+ TRACE_IRQS_OFF_ENTRY ;\
/* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
l.addi r30,r0,-1 ;\
l.sw PT_ORIG_GPR11(r1),r30
@@ -557,9 +613,6 @@ _string_syscall_return:
.align 4
ENTRY(_sys_call_handler)
- /* syscalls run with interrupts enabled */
- ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp
-
/* r1, EPCR, ESR a already saved */
l.sw PT_GPR2(r1),r2
/* r3-r8 must be saved because syscall restart relies
@@ -597,6 +650,10 @@ ENTRY(_sys_call_handler)
/* l.sw PT_GPR30(r1),r30 */
_syscall_check_trace_enter:
+ /* syscalls run with interrupts enabled */
+ TRACE_IRQS_ON_SYSCALL
+ ENABLE_INTERRUPTS(r29) // enable interrupts, r29 is temp
+
/* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
l.lwz r30,TI_FLAGS(r10)
l.andi r30,r30,_TIF_SYSCALL_TRACE
@@ -657,6 +714,7 @@ _syscall_check_trace_leave:
_syscall_check_work:
/* Here we need to disable interrupts */
DISABLE_INTERRUPTS(r27,r29)
+ TRACE_IRQS_OFF
l.lwz r30,TI_FLAGS(r10)
l.andi r30,r30,_TIF_WORK_MASK
l.sfne r30,r0
@@ -871,6 +929,7 @@ UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
_resume_userspace:
DISABLE_INTERRUPTS(r3,r4)
+ TRACE_IRQS_OFF
l.lwz r4,TI_FLAGS(r10)
l.andi r13,r4,_TIF_WORK_MASK
l.sfeqi r13,0
@@ -909,6 +968,15 @@ _work_pending:
l.lwz r8,PT_GPR8(r1)
_restore_all:
+#ifdef CONFIG_TRACE_IRQFLAGS
+ l.lwz r4,PT_SR(r1)
+ l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
+ l.sfeq r3,r0 /* skip trace if irqs were off */
+ l.bf skip_hardirqs_on
+ l.nop
+ TRACE_IRQS_ON
+skip_hardirqs_on:
+#endif
RESTORE_ALL
/* This returns to userspace code */
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH 13/13] openrisc: add tick timer multicore sync logic
2017-08-30 21:58 [PATCH 00/13] OpenRISC SMP Support Stafford Horne
` (11 preceding siblings ...)
2017-08-30 22:03 ` [PATCH 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
@ 2017-08-30 22:03 ` Stafford Horne
12 siblings, 0 replies; 34+ messages in thread
From: Stafford Horne @ 2017-08-30 22:03 UTC (permalink / raw)
To: LKML
Cc: Openrisc, Stafford Horne, Jonas Bonn, Stefan Kristiansson,
Jan Henrik Weinstock, James Hogan, Matt Redfearn, Thomas Gleixner
In case timers are not in sync when cpus start (i.e. hot plug / offset
resets) we need to synchronize the secondary cpus internal timer with
the main cpu. This is needed as in OpenRISC SMP there is only one
clocksource registered which reads from the same ttcr register on each
cpu.
This synchronization routine heavily borrows from mips implementation that
does something similar.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
arch/openrisc/include/asm/or1k-timer.h | 27 ++++++++
arch/openrisc/kernel/Makefile | 2 +-
arch/openrisc/kernel/smp.c | 15 +++--
arch/openrisc/kernel/sync-timer.c | 120 +++++++++++++++++++++++++++++++++
arch/openrisc/kernel/time.c | 15 ++++-
5 files changed, 171 insertions(+), 8 deletions(-)
create mode 100644 arch/openrisc/include/asm/or1k-timer.h
create mode 100644 arch/openrisc/kernel/sync-timer.c
diff --git a/arch/openrisc/include/asm/or1k-timer.h b/arch/openrisc/include/asm/or1k-timer.h
new file mode 100644
index 000000000000..744341b22336
--- /dev/null
+++ b/arch/openrisc/include/asm/or1k-timer.h
@@ -0,0 +1,27 @@
+/*
+ * OpenRISC timer API
+ *
+ * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2017 by Stafford Horne (shorne@gmail.com)
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_OR1K_TIMER_H
+#define __ASM_OR1K_TIMER_H
+
+#include <linux/compiler.h>
+
+void openrisc_timer_set(unsigned long count);
+void openrisc_timer_set_next(unsigned long delta);
+
+#ifdef CONFIG_SMP
+void synchronise_count_master(int cpu);
+void synchronise_count_slave(int cpu);
+#else
+static inline void synchronise_count_master(int cpu) {}
+static inline void synchronise_count_slave(int cpu) {}
+#endif
+
+#endif /* __ASM_OR1K_TIMER_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index b4b51a07016a..9028e5a1fdd7 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -8,7 +8,7 @@ obj-y := setup.o or32_ksyms.o process.o dma.o \
traps.o time.o irq.o entry.o ptrace.o signal.o \
sys_call_table.o unwinder.o
-obj-$(CONFIG_SMP) += smp.o
+obj-$(CONFIG_SMP) += smp.o sync-timer.o
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_OF) += prom.o
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index b349d6cb498f..a3f9f2f5d5d9 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -18,6 +18,7 @@
#include <asm/mmu_context.h>
#include <asm/tlbflush.h>
#include <asm/cacheflush.h>
+#include <asm/or1k-timer.h>
static void (*smp_cross_call)(const struct cpumask *, unsigned int);
@@ -92,13 +93,15 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
ret = boot_secondary(cpu, idle);
if (ret == 0) {
- wait_for_completion_timeout(&cpu_running,
- msecs_to_jiffies(1000));
- if (!cpu_online(cpu))
- ret = -EIO;
+ if (!wait_for_completion_timeout(&cpu_running,
+ msecs_to_jiffies(1000))) {
+ pr_crit("CPU%u: failed to start\n", cpu);
+ return -EIO;
+ }
+ synchronise_count_master(cpu);
}
- return ret;
+ return 0;
}
extern void openrisc_clockevent_init(void);
@@ -128,6 +131,8 @@ asmlinkage __init void secondary_start_kernel(void)
set_cpu_online(cpu, true);
complete(&cpu_running);
+ synchronise_count_slave(cpu);
+
local_irq_enable();
preempt_disable();
diff --git a/arch/openrisc/kernel/sync-timer.c b/arch/openrisc/kernel/sync-timer.c
new file mode 100644
index 000000000000..7af9f20b7fad
--- /dev/null
+++ b/arch/openrisc/kernel/sync-timer.c
@@ -0,0 +1,120 @@
+/*
+ * OR1K timer synchronisation
+ *
+ * Based on work from MIPS implementation.
+ *
+ * All CPUs will have their count registers synchronised to the CPU0 next time
+ * value. This can cause a small timewarp for CPU0. All other CPU's should
+ * not have done anything significant (but they may have had interrupts
+ * enabled briefly - prom_smp_finish() should not be responsible for enabling
+ * interrupts...)
+ */
+
+#include <linux/kernel.h>
+#include <linux/irqflags.h>
+#include <linux/cpumask.h>
+
+#include <asm/or1k-timer.h>
+#include <asm/timex.h>
+#include <linux/atomic.h>
+#include <asm/barrier.h>
+
+#include <asm/spr.h>
+
+static unsigned int initcount;
+static atomic_t count_count_start = ATOMIC_INIT(0);
+static atomic_t count_count_stop = ATOMIC_INIT(0);
+
+#define COUNTON 100
+#define NR_LOOPS 3
+
+void synchronise_count_master(int cpu)
+{
+ int i;
+ unsigned long flags;
+
+ pr_info("Synchronize counters for CPU %u: ", cpu);
+
+ local_irq_save(flags);
+
+ /*
+ * We loop a few times to get a primed instruction cache,
+ * then the last pass is more or less synchronised and
+ * the master and slaves each set their cycle counters to a known
+ * value all at once. This reduces the chance of having random offsets
+ * between the processors, and guarantees that the maximum
+ * delay between the cycle counters is never bigger than
+ * the latency of information-passing (cachelines) between
+ * two CPUs.
+ */
+
+ for (i = 0; i < NR_LOOPS; i++) {
+ /* slaves loop on '!= 2' */
+ while (atomic_read(&count_count_start) != 1)
+ mb();
+ atomic_set(&count_count_stop, 0);
+ smp_wmb();
+
+ /* Let the slave writes its count register */
+ atomic_inc(&count_count_start);
+
+ /* Count will be initialised to current timer */
+ if (i == 1)
+ initcount = get_cycles();
+
+ /*
+ * Everyone initialises count in the last loop:
+ */
+ if (i == NR_LOOPS-1)
+ openrisc_timer_set(initcount);
+
+ /*
+ * Wait for slave to leave the synchronization point:
+ */
+ while (atomic_read(&count_count_stop) != 1)
+ mb();
+ atomic_set(&count_count_start, 0);
+ smp_wmb();
+ atomic_inc(&count_count_stop);
+ }
+ /* Arrange for an interrupt in a short while */
+ openrisc_timer_set_next(COUNTON);
+
+ local_irq_restore(flags);
+
+ /*
+ * i386 code reported the skew here, but the
+ * count registers were almost certainly out of sync
+ * so no point in alarming people
+ */
+ pr_cont("done.\n");
+}
+
+void synchronise_count_slave(int cpu)
+{
+ int i;
+
+ /*
+ * Not every cpu is online at the time this gets called,
+ * so we first wait for the master to say everyone is ready
+ */
+
+ for (i = 0; i < NR_LOOPS; i++) {
+ atomic_inc(&count_count_start);
+ while (atomic_read(&count_count_start) != 2)
+ mb();
+
+ /*
+ * Everyone initialises count in the last loop:
+ */
+ if (i == NR_LOOPS-1)
+ openrisc_timer_set(initcount);
+
+ atomic_inc(&count_count_stop);
+ while (atomic_read(&count_count_stop) != 2)
+ mb();
+ }
+ /* Arrange for an interrupt in a short while */
+ openrisc_timer_set_next(COUNTON);
+}
+#undef NR_LOOPS
diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c
index ab04eaedbf8d..6baecea27080 100644
--- a/arch/openrisc/kernel/time.c
+++ b/arch/openrisc/kernel/time.c
@@ -27,8 +27,14 @@
#include <asm/cpuinfo.h>
-static int openrisc_timer_set_next_event(unsigned long delta,
- struct clock_event_device *dev)
+/* Test the timer ticks to count, used in sync routine */
+inline void openrisc_timer_set(unsigned long count)
+{
+ mtspr(SPR_TTCR, count);
+}
+
+/* Set the timer to trigger in delta cycles */
+inline void openrisc_timer_set_next(unsigned long delta)
{
u32 c;
@@ -44,7 +50,12 @@ static int openrisc_timer_set_next_event(unsigned long delta,
* Keep timer in continuous mode always.
*/
mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
+}
+static int openrisc_timer_set_next_event(unsigned long delta,
+ struct clock_event_device *dev)
+{
+ openrisc_timer_set_next(delta);
return 0;
}
--
2.13.5
^ permalink raw reply related [flat|nested] 34+ messages in thread