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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 5r7F6lGWOFMHoDJf+p2o7p4jv6tEYHCkYTZSTJUE/HcTeCTl4Z4p2pFNAsnKEc2X9CBCbq4bVedq6bNnBvMgh5z++CEEsi2wsjAlIOasxbe5zVVTmo6pRshcApzdSBveR4cufG5cZz+wk2AyQ33m6rKyMXd4JkNCsMm1lH5KqtLBGtNEr7EP79U6+/KBMQHIX5VYoKQb/tac6AG2D3ysFdye8v04PFpEKwWPte3nsAJnJlGfqGcZJ3gS1iQO9JQiH9YLy79Znt8kwiJVHj2YoT0iIWVxUQiuaTTc61T+0pnTCreVbrLlwW/EHCyMW8wb6WW5qh66Se0RggTc5HNbOzRY1nZqrFqKlW1olVGGXxB0pMMAB+xMfDDcJkWURKItO9z1ZFO917FB59mD3c9lPgehnW0QsEgkYmJWHONj+Cs= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 61005864-c84f-48b8-7820-08d6b77ed70a X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Apr 2019 15:21:13.1131 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3257 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch series addresses issues with increased NMI latency in newer AMD processors that can result in unknown NMI messages when PMC counters are active. The following fixes are included in this series: - Resolve a race condition when disabling an overflowed PMC counter, specifically when updating the PMC counter with a new value. - Resolve handling of active PMC counter overflows in the perf NMI handler and when to report that the NMI is not related to a PMC. - Remove earlier workaround for spurious NMIs by re-ordering the PMC stop sequence to disable the PMC first and then remove the PMC bit from the active_mask bitmap. As part of disabling the PMC, the code will wait for an overflow to be reset. The last patch re-works the order of when the PMC is removed from the active_mask. There was a comment from a long time ago about having to clear the bit in active_mask before disabling the counter because the perf NMI handler could re-enable the PMC again. Looking at the handler today, I don't see that as possible, hence the reordering. The question will be whether the Intel PMC support will now have issues. There is still support for using x86_pmu_handle_irq() in the Intel core.c file. Also, I couldn't completely get rid of the "running" bit because it is used by arch/x86/events/intel/p4.c. An old commit comment that seems to indicate the p4 code suffered the spurious interrupts: Commit 03e22198d237 ("perf, x86: Handle in flight NMIs on P4 platform"). --- Changes from v3: - Changed nmi.h include from asm/nmi.h to linux/nmi.h. - Let the information about the last patch in the cover letter, but removed the questions which were previously answered. - Removed the RFC tag. Changes from v2 (based on feedback from Peter Z): - Simplified AMD specific disable_all callback by calling the common x86_pmu_disable_all() function and then checking and waiting for reset of and overflowed PMCs. - Removed erroneous check for no active counters in the NMI latency mitigation patch, which effectively nullified commit 63e6be6d98e1. - Reworked x86_pmu_stop() in order to remove 63e6be6d98e1. Changes from v1 (based on feedback from Peter Z): - Created an AMD specific disable_all callback function to handle the disabling of the counters and resolve the race condition - Created an AMD specific handle_irq callback function that invokes the common x86_pmu_handle_irq() function and then performs the NMI latency mitigation. - Take into account the possibility of non-perf NMI sources when applying the mitigation. This patch series is based off of the perf/core branch of tip: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf/core Commit 1a9df9e29c2a ("Merge git://git.kernel.org/pub/scm/linux/kernel/git= /davem/net") Tom Lendacky (3): x86/perf/amd: Resolve race condition when disabling PMC x86/perf/amd: Resolve NMI latency issues for active PMCs x86/perf/amd: Remove need to check "running" bit in NMI handler arch/x86/events/amd/core.c | 139 +++++++++++++++++++++++++++++++++++-- arch/x86/events/core.c | 13 +--- 2 files changed, 137 insertions(+), 15 deletions(-) --=20 2.17.1