Re: [PATCH 5/8] OPP: Allow multiple clocks for a device

Dmitry Osipenko
2022-06-30T09:57:30Z

On 6/30/22 12:52, Viresh Kumar wrote:
> On 30-06-22, 12:13, Dmitry Osipenko wrote:
>> On 6/30/22 03:50, Viresh Kumar wrote:
>>> On 29-06-22, 21:33, Dmitry Osipenko wrote:
>>>> Today I noticed that tegra30-devfreq driver now fails to probe because
>>>> dev_pm_opp_find_freq_ceil() fails with -ERANGE. This patch is guilty for
>>>> that. Could you please take a look?
>
>> We added memory interconnect support to Tegra and since that time only
>> the memory controller can drive the clock rate. All other drivers,
>> including the devfreq, now issue memory bandwidth requests using ICC.
>>
>> In case of the devfreq driver, it's the OPP core that makes the bw
>> request using ICC.
>>
>> But it's the set_freq_table() that fails [2], I see
>> dev_pm_opp_get_opp_count() returns 17, which is correct, and then
>> dev_pm_opp_find_freq_ceil(freq=0) returns freq=1, which shall be
>> freq=12750000.
>
> I am confused, you said earlier that it is failing with -ERANGE, but
> now it is a bad freq value ?
>
> Which one of these it is ?
>
> The problem I see is here though, because of which I was asking you
> the question earlier:
>
> - tegra30-devfreq driver calls devm_pm_opp_of_add_table_noclk(), i.e.
> clk_count == 0.
>
> - _read_rate() (in drivers/opp/of.c) skips reading any opp-hz
> properties if clk_count is 0.
>
> - And so you can get -ERANGE or some other error.
>
> Can you please see where we are failing. Also I don't see how freq can
> get set to 1 currently.
>

The set_freq_table() gets available freqs using
dev_pm_opp_find_freq_ceil() iteration.

The first dev_pm_opp_find_freq_ceil(freq=0) succeeds and returns ceil
freq=1.

The second dev_pm_opp_find_freq_ceil(freq=1) fails with -ERANGE.

I haven't looked yet at why freq is set to 1.

--
Best regards,
Dmitry