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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id e6-20020a17090301c600b001ecf8659bd7sm10061883plh.257.2024.05.07.07.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 May 2024 07:07:42 -0700 (PDT) From: Zong Li To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, tjeznach@rivosinc.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, jgg@ziepe.ca, kevin.tian@intel.com, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-riscv@lists.infradead.org Cc: Zong Li Subject: [RFC 0/6] RISC-V IOMMU HPM and nested IOMMU support Date: Tue, 7 May 2024 22:07:31 +0800 Message-Id: X-Mailer: git-send-email 2.17.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: This series includes RISC-V IOMMU hardware performance monitor and nested IOMMU support. It also introduces operations for the g-stage table, which are required for nested IOMMU. This patch set is implemented on top of the RISC-V IOMMU v4 series [1], and it will be submitted as an RFC until the RISC-V IOMMU has been merged. Additionally, it will be updated as needed when a new version of the RISC-V IOMMU series is posted. [1] link: https://lists.infradead.org/pipermail/linux-riscv/2024-May/053708.html Zong Li (6): iommu/riscv: Add RISC-V IOMMU PMU support iommu/riscv: Support HPM and interrupt handling iommu/riscv: support GSCID iommu/riscv: support nested iommu for getting iommu hardware information iommu/riscv: support nested iommu for creating domains owned by userspace iommu/riscv: support nested iommu for flushing cache drivers/iommu/riscv/Makefile | 4 +- drivers/iommu/riscv/iommu-bits.h | 22 ++ drivers/iommu/riscv/iommu-pmu.c | 477 ++++++++++++++++++++++++++++++ drivers/iommu/riscv/iommu.c | 481 +++++++++++++++++++++++++++++-- drivers/iommu/riscv/iommu.h | 8 + include/uapi/linux/iommufd.h | 39 +++ 6 files changed, 1002 insertions(+), 29 deletions(-) create mode 100644 drivers/iommu/riscv/iommu-pmu.c -- 2.17.1