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Fri, 13 Jun 2025 08:05:21 -0700 (PDT) Received: from geday ([2804:7f2:800b:838f::dead:c001]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2365deca008sm15308325ad.193.2025.06.13.08.05.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jun 2025 08:05:20 -0700 (PDT) Date: Fri, 13 Jun 2025 12:05:15 -0300 From: Geraldo Nascimento To: linux-rockchip@lists.infradead.org Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Vinod Koul , Kishon Vijay Abraham I , linux-phy@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RESEND RFC PATCH v4 0/5] PCI: rockchip: Improve driver quality Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline During a 30-day debugging-run fighting quirky PCIe devices on RK3399 some quality improvements began to take form and this is my attempt at upstreaming it. It will ensure maximum chance of retraining to Gen2 5.0GT/s, on all four lanes and plus if anybody is debugging the PHY they'll now get real values from TEST_I[3:0] for every TEST_ADDR[4:0] without risk of locking up kernel like with present broken async strobe TEST_WRITE. --- V3 -> V4: fix setting-up of TLS in Link Control and Status Register 2, also adjust commit titles V2 -> V3: correctly clean-up with standard PCIe defines as per Bjorn's suggestion V1 -> V2: use standard PCIe defines as suggested by Bjorn Geraldo Nascimento (5): PCI: rockchip: Use standard PCIe defines PCI: rockchip: Drop unused custom registers and bitfields PCI: rockchip: Set Target Link Speed before retraining phy: rockchip-pcie: Enable all four lanes phy: rockchip-pcie: Adjust read mask and write drivers/pci/controller/pcie-rockchip-host.c | 48 +++++++++++---------- drivers/pci/controller/pcie-rockchip.h | 11 +---- drivers/phy/rockchip/phy-rockchip-pcie.c | 16 ++++--- 3 files changed, 36 insertions(+), 39 deletions(-) -- 2.49.0