From: adrianhoyin.ng@altera.com
To: dinguyen@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: adrianhoyin.ng@altera.com
Subject: [PATCH v2 0/2] Add SMMU-V3-PMCG and L2/L3 cache nodes in Agilex5 DTSI
Date: Tue, 17 Jun 2025 16:58:53 +0800 [thread overview]
Message-ID: <cover.1750150179.git.adrianhoyin.ng@altera.com> (raw)
From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
This patchset include the following changes:
-Add SMMU-V3-PMCG node for Agilex5
-Add L2 and L3 cache node for Agilex5
v2:
-Move MMIO nodes into soc@0
Adrian Ng Ho Yin (2):
arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes
arm64: dts: socfpga: agilex5: Add L2 and L3 cache
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
--
2.49.GIT
next reply other threads:[~2025-06-17 8:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-17 8:58 adrianhoyin.ng [this message]
2025-06-17 8:58 ` [PATCH v2 1/2] arm64: dts: socfpga: agilex5: Add SMMU-V3-PMCG nodes adrianhoyin.ng
2025-06-17 8:58 ` [PATCH v2 2/2] arm64: dts: socfpga: agilex5: Add L2 and L3 cache adrianhoyin.ng
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