[PATCH 0/4] Add 4-bit SPI bus width on target devices

[PATCH 0/4] Add 4-bit SPI bus width on target devices

[yankei.fong]

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add SPI bus width properties to correctly describe the hardware on the following devices:
 - Stratix10
 - Agilex
 - Agilex5
 - N5X

Fong, Yan Kei (4):
  arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
 4 files changed, 8 insertions(+)

-- 
2.25.1

[PATCH 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width

[yankei.fong]

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the n5x device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 7952c7f47cc2..0034a4897220 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -93,6 +93,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1

Re: [PATCH 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width

[Dinh Nguyen]

On 6/24/25 01:52, yankei.fong@altera.com wrote:
> From: "Fong, Yan Kei" <yan.kei.fong@altera.com>
> 
> Add spi-tx-bus-width and spi-rx-bus-width properties with
> value 4 to the n5x device tree.
> This update configures the SPI controller to use a 4-bit
> bus width for both transmission and reception,
> potentially improving SPI throughput and
> matching the hardware capabilities more closely.

Please use 80 columns for your commit message! Like this:

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
n5x device tree. This update configures the SPI controller to use a
4-bit bus width for both transmission and reception, potentially 
improving SPI throughput and matching the hardware capabilities more 
closely.

Doesn't the above make it much easier to read? Please do this fall your 
patches from now on!

Dinh

[PATCH 2/4] arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width

[yankei.fong]

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the stratix10 device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 4eee777ef1a1..6ff6ea0c6b2d 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -190,6 +190,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1

[PATCH 3/4] arm64: dts: socfpga: agilex: Add 4-bit SPI bus width

[yankei.fong]

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the agilex device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..9ee312bae8d2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -116,6 +116,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1

[PATCH 4/4] arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

[yankei.fong]

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the agilex5 device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index d3b913b7902c..853e260c3976 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -57,6 +57,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1

Re: [PATCH 0/4] Add 4-bit SPI bus width on target devices

[Dinh Nguyen]

On 6/24/25 01:52, yankei.fong@altera.com wrote:
> From: "Fong, Yan Kei" <yan.kei.fong@altera.com>
> 
> Add SPI bus width properties to correctly describe the hardware on the following devices:
>   - Stratix10
>   - Agilex
>   - Agilex5
>   - N5X
> 
> Fong, Yan Kei (4):
>    arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
>    arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
>    arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
>    arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
> 
>   arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
>   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
>   arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
>   arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
>   4 files changed, 8 insertions(+)
> 

This is for the QSPI driver right? I don't even see the driver using 
this property. So how would this help?

[PATCH 0/4] Add 4-bit SPI bus width on target devices

[yankei.fong]

From: Fong, Yan Kei <yan.kei.fong@altera.com>

The changes required for the QSPI subsystem. With this implementation, the
read performance will be greater compare to single bus width when trying
to read the QSPI flash chips. Below is the test results:

$cat /sys/kernel/debug/spi-nor/spi0.0/params
...
...
opcodes
read 0x6c  -> from micron QSPI spec, 6c indicates quad output fast read
...
...
protocols
read 1S-1S-4S

RE: [PATCH 0/4] Add 4-bit SPI bus width on target devices

[Fong, Yan Kei]

> On 6/24/25 01:52, yankei.fong@altera.com wrote:
> > From: "Fong, Yan Kei" <yan.kei.fong@altera.com>
> >
> > Add SPI bus width properties to correctly describe the hardware on the
> following devices:
> >   - Stratix10
> >   - Agilex
> >   - Agilex5
> >   - N5X
> >
> > Fong, Yan Kei (4):
> >    arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
> >    arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
> >    arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
> >    arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
> >
> >   arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
> >   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
> >   arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
> >   arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
> >   4 files changed, 8 insertions(+)
> >
> 
> This is for the QSPI driver right? I don't even see the driver using this property.
> So how would this help?

Yes, it's for QSPI driver. The bindings (spi-tx-bus-width and spi-rx-bus-width) are defined in Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml. They are read in of_spi_parse_dt() which is ultimately called from spi_register_controller().