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Mon, 11 Aug 2025 16:00:02 -0700 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 0/5] Disable ATS via iommu during PCI resets Date: Mon, 11 Aug 2025 15:59:07 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0002256F:EE_|MW4PR12MB5668:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f8ea4cf-29d7-40be-522a-08ddd92ad962 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?pzEzXUFOtKGQTzg0K5HT9XQXN6lUJQC9VkBs7a7HgH10VsYVSuOGucrtmoA7?= =?us-ascii?Q?OzQmduWgiMGBCj0hj6VlqrsOXuB9Q8L60MMJX2xOVDrRThPSnTrGgLDxJ7D3?= =?us-ascii?Q?lQPjXV0Ckie4o9XOlK59h3O80jAxnTHFre0lftzL0M6iZVJzpr0m48633HiG?= =?us-ascii?Q?TAnUkJ3rIT3cgEu4ToIX1GPTqCLfYR57nivSf28+tItbsFFrpcEGc1941u58?= =?us-ascii?Q?aveKNEzM0ZFJP5a9fqWFg0FWq1woYg1dQH2ZAeHqJPAeGixy5efx/nxKczfT?= =?us-ascii?Q?/S9smgHxIPf+CPo7t1EEJfCz7zQHZFeFGZpIXcP1sSdPw9Np87DjbDi7Jb4G?= =?us-ascii?Q?QIn3SQ2tp2M7Qo9pApYWsgAbnrQIq5H9yHjNWKxm8riA0s9wf8A/A0DY5xOA?= =?us-ascii?Q?cE6ObHOsejfyv9HU96lhX1SMQZq+CQSYgp1v1tLQNli+xrHz2SGXKY8dlRQO?= =?us-ascii?Q?tZWnZX4LZetNjhUStaWWnQppwJSdoTO8W7dLZhPZRU7g7QSmm+ZBG1cbolQh?= =?us-ascii?Q?F9pQD+tLGisY2kmx21PjIktEu+eKBD9e4XCpWN6UlwrwVwN/AxHDQbD2bfyG?= =?us-ascii?Q?8S9vH82o25FT8rKn8et+0ypD8tajqXq33Y/c+7f0Cp+zJpgr/uxbObJWBQCh?= =?us-ascii?Q?ZjgLHWsjy5MpGviBuENRAPNcWYm9mmrortxqwOUBc1Xwp+6C/BawsChNeJS4?= =?us-ascii?Q?T5zP3YCak5+5sBrL2WOk/9UtOD1Hd0Xz8OnpZNTh/LlxWLI/8dl5vJkwiAey?= =?us-ascii?Q?L6Gkj4crNfTAdhiL1u5v7r0GttJXzCuHflIFwRVxybit4n7u3TJd+KnBFHLF?= =?us-ascii?Q?Ex/amY0L0P69GdM7zRvf2WarkKyMZhPLQ9RvFNUSizqvD5/90X9dhQkV4ZYd?= =?us-ascii?Q?KTOOTn4OYcoh2krH5uSgxr/n9HYsIIYsec7Q4dOwOyvGjw2cUo5XhM8im2K2?= =?us-ascii?Q?4FO8sETd3m/ctUQ2HT+k9RCNdf9bL9envSfpyyAtlT2Z9Zq25NKsivdubdRL?= =?us-ascii?Q?1bGy4xAsm9V2E/1tNA2Xy7yCB2XrJ2opIUNC5KL4wyfS/vyGxkUipTuuXoPF?= =?us-ascii?Q?mWi0gwkxuCR9/prsMZHtYHWwkLdvBt8XXajN/hvxUexgrM40w2lEHzOaGHjr?= =?us-ascii?Q?Yt+8eA44wtrkL2S92JKW8B/ahAsBn2vvJS67sCGHPSwTN8Fr7iGuu0c9J/nq?= =?us-ascii?Q?rbOFA/NEOfSe3BTs+pNGUzYuvJd4vj2hJHsdoWFWsLhsnbWLVVhC16YsrdIK?= =?us-ascii?Q?tim3taBa+PNw8Bd16qHLlBZ7XZ0vAk+xh0DalNJwMQZ5LwZwRVmSyNAxyeMW?= =?us-ascii?Q?yEv1fKnvxniwb0+HsR7uM915TP85IYLxlq8FtJsVKJ99SoKCUMDBVKY6LGLZ?= =?us-ascii?Q?8Rsyw1iszKkXtZX2MsGwEJQoYgZCSAYmissea+j8kLsmfBmlbfXqijDFF97J?= =?us-ascii?Q?ii9ZZdwLIQA/iKcEniZTgdvMfQtyonMHcidMt+1Cz3FOTWBH8ZWyECxFeHzM?= =?us-ascii?Q?6lPWRVwj4BttYKmffyxYhB4ArFjlElmuQfBWJkalOjW7wHz3ifpjdNeGLg?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(376014)(1800799024)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Aug 2025 23:00:21.3643 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f8ea4cf-29d7-40be-522a-08ddd92ad962 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0002256F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB5668 Hi all, PCIe permits a device to ignore ATS invalidation TLPs, while processing a reset. This creates a problem visible to the OS where an ATS invalidation command will time out: e.g. an SVA domain will have no coordination with a reset event and can racily issue ATS invalidations to a resetting device. The OS should do something to mitigate this as we do not want production systems to be reporting critical ATS failures, especially in a hypervisor environment. Broadly, OS could arrange to ignore the timeouts, block page table mutations to prevent invalidations, or disable and block ATS. The PCIe spec in sec 10.3.1 IMPLEMENTATION NOTE recommends to disable and block ATS before initiating a Function Level Reset. It also mentions that other reset methods could have the same vulnerability as well. Provide a callback from the PCI subsystem that will enclose the reset and have the iommu core temporarily change domains to group->blocking_domain, so IOMMU drivers would fence any incoming ATS queries, synchronously stop issuing new ATS invalidations, and wait for existing ATS invalidations to complete. Doing this can avoid any ATS invaliation timeouts. When a device is resetting, any new domain attachment should be deferred, until the reset is finished, to prevent ATS activity from being activated between the two callback functions. Introduce a new pending_reset flag to allow iommu core to cache the target domains in the SW level but bypass the driver-level attachment. Later, iommu_dev_reset_done() will re-attach these soft-attached domains via __iommu_attach_device/set_group_pasid(). Finally, apply these iommu_dev_reset_prepare/done() functions in the PCI reset functions. This is on Github: https://github.com/nicolinc/iommufd/commits/iommu_dev_reset-v3 Changelog v3 * Add Reviewed-by from Jason * [iommu] Add a fast return in iommu_deferred_attach() * [iommu] Update kdocs, inline comments, and commit logs * [iommu] Use group->blocking_domain v.s. ops->blocked_domain * [iommu] Drop require_direct, iommu_group_get(), and xa_lock() * [iommu] Set the pending_reset flag after RID/PASID domain setups * [iommu] Do not bypass PASID domains when RID domain is already the blocking_domain * [iommu] Add iommu_get_domain_for_dev_locked to correctly return the blocking_domain v2 https://lore.kernel.org/all/cover.1751096303.git.nicolinc@nvidia.com/ * [iommu] Update kdocs, inline comments, and commit logs * [iommu] Replace long-holding group->mutex with a pending_reset flag * [pci] Abort reset routines if iommu_dev_reset_prepare() fails * [pci] Apply the same vulnerability fix to other reset functions v1 https://lore.kernel.org/all/cover.1749494161.git.nicolinc@nvidia.com/ Thanks Nicolin Nicolin Chen (5): iommu: Lock group->mutex in iommu_deferred_attach iommu: Pass in gdev to __iommu_device_set_domain iommu: Add iommu_get_domain_for_dev_locked() helper iommu: Introduce iommu_dev_reset_prepare() and iommu_dev_reset_done() pci: Suspend iommu function prior to resetting a device include/linux/iommu.h | 13 ++ .../arm/arm-smmu-v3/arm-smmu-v3-iommufd.c | 2 +- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 9 +- drivers/iommu/arm/arm-smmu/qcom_iommu.c | 2 +- drivers/iommu/dma-iommu.c | 2 +- drivers/iommu/fsl_pamu_domain.c | 2 +- drivers/iommu/iommu.c | 205 +++++++++++++++++- drivers/iommu/ipmmu-vmsa.c | 2 +- drivers/iommu/msm_iommu.c | 2 +- drivers/iommu/mtk_iommu.c | 2 +- drivers/iommu/omap-iommu.c | 2 +- drivers/iommu/tegra-smmu.c | 2 +- drivers/pci/pci-acpi.c | 17 +- drivers/pci/pci.c | 68 +++++- drivers/pci/quirks.c | 23 +- 15 files changed, 323 insertions(+), 30 deletions(-) -- 2.43.0