[PATCH v2 0/4] Add 4-bit SPI bus width on target devices

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* [PATCH v2 0/4] Add 4-bit SPI bus width on target devices
@ 2025-09-11  1:37 yankei.fong
  2025-09-11  1:37 ` [PATCH v2 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width yankei.fong
                   ` (8 more replies)
  0 siblings, 9 replies; 14+ messages in thread
From: yankei.fong @ 2025-09-11  1:37 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add SPI bus width properties to correctly describe the hardware on the
following devices:
- Stratix10
- Agilex
- Agilex5
- N5X

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
changes in v2:
	- rewrite the commit message body to align with 80 characters.
	- add additional reviewer
---
Fong, Yan Kei (4):
  arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
 4 files changed, 8 insertions(+)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v2 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
@ 2025-09-11  1:37 ` yankei.fong
  2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
  2025-09-11  1:37 ` [PATCH v2 2/4] arm64: dts: socfpga: stratix10: " yankei.fong
                   ` (7 subsequent siblings)
  8 siblings, 1 reply; 14+ messages in thread
From: yankei.fong @ 2025-09-11  1:37 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the n5x 
device tree. This update configures the SPI controller to use a 4-bit bus width
for both transmission and reception, potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 7952c7f47cc2..0034a4897220 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -93,6 +93,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v3 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  2025-09-11  1:37 ` [PATCH v2 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width yankei.fong
@ 2025-09-11  1:58   ` Fong, Yan Kei
  0 siblings, 0 replies; 14+ messages in thread
From: Fong, Yan Kei @ 2025-09-11  1:58 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the n5x 
device tree. This update configures the SPI controller to use a 4-bit bus width
for both transmission and reception, potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index 7952c7f47cc2..0034a4897220 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -93,6 +93,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v2 2/4] arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
  2025-09-11  1:37 ` [PATCH v2 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width yankei.fong
@ 2025-09-11  1:37 ` yankei.fong
  2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
  2025-09-11  1:37 ` [PATCH v2 3/4] arm64: dts: socfpga: agilex: " yankei.fong
                   ` (6 subsequent siblings)
  8 siblings, 1 reply; 14+ messages in thread
From: yankei.fong @ 2025-09-11  1:37 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
stratix10 device tree. This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception, potentially improving SPI
throughput and matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 4eee777ef1a1..6ff6ea0c6b2d 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -190,6 +190,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v3 2/4] arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  2025-09-11  1:37 ` [PATCH v2 2/4] arm64: dts: socfpga: stratix10: " yankei.fong
@ 2025-09-11  1:58   ` Fong, Yan Kei
  0 siblings, 0 replies; 14+ messages in thread
From: Fong, Yan Kei @ 2025-09-11  1:58 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
stratix10 device tree. This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception, potentially improving SPI
throughput and matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 4eee777ef1a1..6ff6ea0c6b2d 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -190,6 +190,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v2 3/4] arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
  2025-09-11  1:37 ` [PATCH v2 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width yankei.fong
  2025-09-11  1:37 ` [PATCH v2 2/4] arm64: dts: socfpga: stratix10: " yankei.fong
@ 2025-09-11  1:37 ` yankei.fong
  2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
  2025-09-11  1:37 ` [PATCH v2 4/4] arm64: dts: socfpga: agilex5: " yankei.fong
                   ` (5 subsequent siblings)
  8 siblings, 1 reply; 14+ messages in thread
From: yankei.fong @ 2025-09-11  1:37 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex
device tree. This update configures the SPI controller to use a 4-bit bus width
for both transmission and reception, potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..9ee312bae8d2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -116,6 +116,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v3 3/4] arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  2025-09-11  1:37 ` [PATCH v2 3/4] arm64: dts: socfpga: agilex: " yankei.fong
@ 2025-09-11  1:58   ` Fong, Yan Kei
  0 siblings, 0 replies; 14+ messages in thread
From: Fong, Yan Kei @ 2025-09-11  1:58 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the agilex
device tree. This update configures the SPI controller to use a 4-bit bus width
for both transmission and reception, potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index b31cfa6b802d..9ee312bae8d2 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -116,6 +116,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v2 4/4] arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
                   ` (2 preceding siblings ...)
  2025-09-11  1:37 ` [PATCH v2 3/4] arm64: dts: socfpga: agilex: " yankei.fong
@ 2025-09-11  1:37 ` yankei.fong
  2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
  2025-09-11  1:58 ` [PATCH v2 0/4] Add 4-bit SPI bus width on target devices Fong, Yan Kei
                   ` (4 subsequent siblings)
  8 siblings, 1 reply; 14+ messages in thread
From: yankei.fong @ 2025-09-11  1:37 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

From: "Fong, Yan Kei" <yan.kei.fong@altera.com>

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex5 device tree. This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception, potentially improving SPI
throughput and matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index d3b913b7902c..853e260c3976 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -57,6 +57,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v3 4/4] arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
  2025-09-11  1:37 ` [PATCH v2 4/4] arm64: dts: socfpga: agilex5: " yankei.fong
@ 2025-09-11  1:58   ` Fong, Yan Kei
  0 siblings, 0 replies; 14+ messages in thread
From: Fong, Yan Kei @ 2025-09-11  1:58 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
agilex5 device tree. This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception, potentially improving SPI
throughput and matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index d3b913b7902c..853e260c3976 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -57,6 +57,8 @@ flash@0 {
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 14+ messages in thread

* [PATCH v2 0/4] Add 4-bit SPI bus width on target devices
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
                   ` (3 preceding siblings ...)
  2025-09-11  1:37 ` [PATCH v2 4/4] arm64: dts: socfpga: agilex5: " yankei.fong
@ 2025-09-11  1:58 ` Fong, Yan Kei
  2025-09-11  2:21 ` [PATCH v3 " Fong, Yan Kei
                   ` (3 subsequent siblings)
  8 siblings, 0 replies; 14+ messages in thread
From: Fong, Yan Kei @ 2025-09-11  1:58 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

Add SPI bus width properties to correctly describe the hardware on the
following devices:
- Stratix10
- Agilex
- Agilex5
- N5X

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
changes in v2:
	- rewrite the commit message body to align with 80 characters.
	- add additional reviewer
---
Fong, Yan Kei (4):
  arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
 4 files changed, 8 insertions(+)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v3 0/4] Add 4-bit SPI bus width on target devices
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
                   ` (4 preceding siblings ...)
  2025-09-11  1:58 ` [PATCH v2 0/4] Add 4-bit SPI bus width on target devices Fong, Yan Kei
@ 2025-09-11  2:21 ` Fong, Yan Kei
  2025-09-12 12:30 ` Dinh Nguyen
                   ` (2 subsequent siblings)
  8 siblings, 0 replies; 14+ messages in thread
From: Fong, Yan Kei @ 2025-09-11  2:21 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

Add SPI bus width properties to correctly describe the hardware on the
following devices:
- Stratix10
- Agilex
- Agilex5
- N5X

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
changes in v3:
	- remove the unalign email shown in the commit message body
changes in v2:
	- rewrite the commit message body to align with 80 characters.
	- add additional reviewer
---
Fong, Yan Kei (4):
  arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
  arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
  arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
 arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
 4 files changed, 8 insertions(+)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 0/4] Add 4-bit SPI bus width on target devices
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
                   ` (5 preceding siblings ...)
  2025-09-11  2:21 ` [PATCH v3 " Fong, Yan Kei
@ 2025-09-12 12:30 ` Dinh Nguyen
  2025-09-17  6:44 ` Fong, Yan Kei
  2025-10-15  3:10 ` Dinh Nguyen
  8 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2025-09-12 12:30 UTC (permalink / raw)
  To: Fong, Yan Kei, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli



On 9/10/25 21:21, Fong, Yan Kei wrote:
> Add SPI bus width properties to correctly describe the hardware on the
> following devices:
> - Stratix10
> - Agilex
> - Agilex5
> - N5X
> 
> Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
> Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
> changes in v3:
> 	- remove the unalign email shown in the commit message body
> changes in v2:
> 	- rewrite the commit message body to align with 80 characters.
> 	- add additional reviewer
>

You have a series of v2 and v3 patches in the same thread. Which ones 
should I look at?



^ permalink raw reply	[flat|nested] 14+ messages in thread

* [PATCH v3 0/4] Add 4-bit SPI bus width on target devices
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
                   ` (6 preceding siblings ...)
  2025-09-12 12:30 ` Dinh Nguyen
@ 2025-09-17  6:44 ` Fong, Yan Kei
  2025-10-15  3:10 ` Dinh Nguyen
  8 siblings, 0 replies; 14+ messages in thread
From: Fong, Yan Kei @ 2025-09-17  6:44 UTC (permalink / raw)
  To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli

> > Add SPI bus width properties to correctly describe the hardware on the
> > following devices:
> > - Stratix10
> > - Agilex
> > - Agilex5
> > - N5X
> > 
> > Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
> > Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> > Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
> > ---
> > changes in v3:
> > 	- remove the unalign email shown in the commit message body
> > changes in v2:
> > 	- rewrite the commit message body to align with 80 characters.
> > 	- add additional reviewer
> > ---
>
> You have a series of v2 and v3 patches in the same thread. Which ones 
> should I look at?

Hi Dinh, you may look at v3 patches. Thank you.

^ permalink raw reply	[flat|nested] 14+ messages in thread

* Re: [PATCH v3 0/4] Add 4-bit SPI bus width on target devices
  2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
                   ` (7 preceding siblings ...)
  2025-09-17  6:44 ` Fong, Yan Kei
@ 2025-10-15  3:10 ` Dinh Nguyen
  8 siblings, 0 replies; 14+ messages in thread
From: Dinh Nguyen @ 2025-10-15  3:10 UTC (permalink / raw)
  To: Fong, Yan Kei, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
	open list, Matthew Gerlach, Khairul Anuar Romli



On 9/17/25 01:44, Fong, Yan Kei wrote:
>>> Add SPI bus width properties to correctly describe the hardware on the
>>> following devices:
>>> - Stratix10
>>> - Agilex
>>> - Agilex5
>>> - N5X
>>>
>>> Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
>>> Reviewed-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>>> Reviewed-by: Matthew Gerlach <matthew.gerlach@altera.com>
>>> ---
>>> changes in v3:
>>> 	- remove the unalign email shown in the commit message body
>>> changes in v2:
>>> 	- rewrite the commit message body to align with 80 characters.
>>> 	- add additional reviewer
>>> ---
>>
>> You have a series of v2 and v3 patches in the same thread. Which ones
>> should I look at?
> 
> Hi Dinh, you may look at v3 patches. Thank you.

Applied!

Thanks,
Dinh

^ permalink raw reply	[flat|nested] 14+ messages in thread

end of thread, other threads:[~2025-10-15  3:10 UTC | newest]

Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-09-11  1:37 [PATCH v2 0/4] Add 4-bit SPI bus width on target devices yankei.fong
2025-09-11  1:37 ` [PATCH v2 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width yankei.fong
2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
2025-09-11  1:37 ` [PATCH v2 2/4] arm64: dts: socfpga: stratix10: " yankei.fong
2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
2025-09-11  1:37 ` [PATCH v2 3/4] arm64: dts: socfpga: agilex: " yankei.fong
2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
2025-09-11  1:37 ` [PATCH v2 4/4] arm64: dts: socfpga: agilex5: " yankei.fong
2025-09-11  1:58   ` [PATCH v3 " Fong, Yan Kei
2025-09-11  1:58 ` [PATCH v2 0/4] Add 4-bit SPI bus width on target devices Fong, Yan Kei
2025-09-11  2:21 ` [PATCH v3 " Fong, Yan Kei
2025-09-12 12:30 ` Dinh Nguyen
2025-09-17  6:44 ` Fong, Yan Kei
2025-10-15  3:10 ` Dinh Nguyen

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