[PATCH 0/4] Add Device Tree binding and nodes for Agilex5/Agilex SOC FCS configuration.

[PATCH 0/4] Add Device Tree binding and nodes for Agilex5/Agilex SOC FCS configuration.

[hangsuan.wang]

From: "Wang, Hang Suan" <hang.suan.wang@altera.com>

This patch series introduces necessary Device Tree (DT) support for the
Soc/Hardware FPGA Crypto Service (fcs) functionality across the Altera
Agilex SoC families. This feature allows the kernel to identify, interact
and communicate with the high-speed FPGA hardware without interruption or
software overhead.

The series structured as follows:
Patch 1: Introduces the core YAML schema binding for a generic agilex5,
soc-fcs-config miscellaneous device.
Patch 2: Add fcs property to the existing stratix10-svc firmware binding.
Patch 3&4: Add the fcs nodes to the respective Agilex5 and Agilex DT files.

---
Notes:
This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

---
Wang, Hang Suan (4):
  dt-bindings: misc: agilex5-soc-fcs-config: Add binding
  dt-bindings: firmware: stratix10-svc: add fcs-config property
  arm64: dts: socfpga: agilex5: add fcs node
  arm64: dts: socfpga: agilex: add fcs node

 .../firmware/intel,stratix10-svc.yaml         |  4 +++
 .../misc/intel,agilex5-soc-fcs-config.yaml    | 32 +++++++++++++++++++
 MAINTAINERS                                   |  5 +++
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  4 +++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  5 +++
 5 files changed, 50 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml

-- 
2.43.7

[PATCH 1/4] dt-bindings: misc: agilex5-soc-fcs-config: Add binding

[hangsuan.wang]

From: "Wang, Hang Suan" <hangsuan.wang@altera.com>

Soc/Hardware FPGA crypto services (fcs) by ensuring optimal performance,
secure isolation, and robust system management. This will allow dedicated
system resources to communicate with the high-speed FPGA hardware without
interruption or software overhead.

This results in faster, more secure, and consistent cryptographic
operations compared to running the services entirely on the
general-purpose CPU.

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Signed-off-by: Wang, Hang Suan <hangsuan.wang@altera.com>
---
---
 .../misc/intel,agilex5-soc-fcs-config.yaml    | 32 +++++++++++++++++++
 MAINTAINERS                                   |  5 +++
 2 files changed, 37 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml

diff --git a/Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml b/Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml
new file mode 100644
index 000000000000..10cd793f8fc5
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/misc/intel,agilex5-soc-fcs-config.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera SoC FPGA Crypto Service features
+
+maintainers:
+  - Wang Hang Suan <hangsuan.wang@altera.com>
+  - Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
+  - Sagar Khadgi <sagar.khadgi@altera.com>
+  - Santosh Male <santosh.male@altera.com>
+  - Mahesh Rao <mahesh.rao@altera.com>
+
+properties:
+  compatible:
+    enum:
+      - intel,agilex5-soc-fcs-config
+      - intel,agilex-soc-fcs-config
+
+additionalProperties: false
+
+required:
+  - compatible
+
+examples:
+  - |
+    fcs_config: fcs-config {
+      compatible = "intel,agilex5-soc-fcs-config";
+    };
+
diff --git a/MAINTAINERS b/MAINTAINERS
index 46126ce2f968..2208d611f73f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -923,6 +923,11 @@ ALPS PS/2 TOUCHPAD DRIVER
 R:	Pali Rohár <pali@kernel.org>
 F:	drivers/input/mouse/alps.*
 
+ALTERA FPGA CRYPTO SERVICE DRIVER
+M:	Hang Suan Wang <hangsuan.wang@altera.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml
+
 ALTERA MAILBOX DRIVER
 M:	Tien Sung Ang <tiensung.ang@altera.com>
 S:	Maintained
-- 
2.43.7

[PATCH 2/4] dt-bindings: firmware: stratix10-svc: add fcs-config property

[hangsuan.wang]

From: "Wang, Hang Suan" <hangsuan.wang@altera.com>

Altera SoC FPGA Crypto Service (fcs) provide hardware crypto features
through mailbox. Fcs property has to be added to compliance with device
tree schema fcs bindings and driver.

Signed-off-by: Wang, Hang Suan <hangsuan.wang@altera.com>
---
---
 .../devicetree/bindings/firmware/intel,stratix10-svc.yaml     | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
index b42cfa78b28b..c105f8dc4b7d 100644
--- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
@@ -62,6 +62,10 @@ properties:
     $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
     description: Optional child node for fpga manager to perform fabric configuration.
 
+  fcs-config:
+    $ref: /schemas/misc/intel,agilex5-soc-fcs-config.yaml
+    description: Optional child node for fcs Fpga Crypto Service (fcs) to perform SoC Crypto Engine.
+
 required:
   - compatible
   - method
-- 
2.43.7

[PATCH 3/4] arm64: dts: socfpga: agilex5: add fcs node

[hangsuan.wang]

From: "Wang, Hang Suan" <hangsuan.wang@altera.com>

Altera new SoC/Hardware FPGA Crypto Service (fcs) provide
hardware crypto features through mailbox. Hence, enable
fcs driver inside the firmware node for agilex devices.

Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@altera.com>
Signed-off-by: Wang, Hang Suan <hangsuan.wang@altera.com>
---
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 1f5d560f97b2..05520f819ea8 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -90,6 +90,11 @@ fpga_mgr: fpga-mgr {
 				compatible = "intel,agilex5-soc-fpga-mgr",
 					     "intel,agilex-soc-fpga-mgr";
 			};
+
+			fcs_config: fcs-config {
+				compatible = "intel,agilex5-soc-fcs-config";
+			};
+
 		};
 	};
 
-- 
2.43.7

[PATCH 4/4] arm64: dts: socfpga: agilex: add fcs node

[hangsuan.wang]

From: "Wang, Hang Suan" <hangsuan.wang@altera.com>

Altera new SoC/Hardware FPGA Crypto Service (fcs) provide
hardware crypto features through mailbox. Hence, enable
fcs driver inside the firmware node for agilex devices.

Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Wang, Hang Suan <hangsuan.wang@altera.com>
---
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 0dfbafde8822..3ee2f7eb7ea3 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -69,6 +69,10 @@ svc {
 			fpga_mgr: fpga-mgr {
 				compatible = "intel,agilex-soc-fpga-mgr";
 			};
+
+			fcs_config: fcs-config {
+				compatible = "intel,agilex-soc-fcs-config";
+			};
 		};
 	};
 
-- 
2.43.7

Re: [PATCH 0/4] Add Device Tree binding and nodes for Agilex5/Agilex SOC FCS configuration.

[Wang, Hang Suan]

Please disregard this submission.
Apologizes for inconvenience caused.

---
On 12/12/2025 7:35 pm, hangsuan.wang@altera.com wrote:
> From: "Wang, Hang Suan" <hang.suan.wang@altera.com>
> 
> This patch series introduces necessary Device Tree (DT) support for the
> Soc/Hardware FPGA Crypto Service (fcs) functionality across the Altera
> Agilex SoC families. This feature allows the kernel to identify, interact
> and communicate with the high-speed FPGA hardware without interruption or
> software overhead.
> 
> The series structured as follows:
> Patch 1: Introduces the core YAML schema binding for a generic agilex5,
> soc-fcs-config miscellaneous device.
> Patch 2: Add fcs property to the existing stratix10-svc firmware binding.
> Patch 3&4: Add the fcs nodes to the respective Agilex5 and Agilex DT files.
> 
> ---
> Notes:
> This patch series is applied on socfpga maintainer's tree
> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
> 
> ---
> Wang, Hang Suan (4):
>    dt-bindings: misc: agilex5-soc-fcs-config: Add binding
>    dt-bindings: firmware: stratix10-svc: add fcs-config property
>    arm64: dts: socfpga: agilex5: add fcs node
>    arm64: dts: socfpga: agilex: add fcs node
> 
>   .../firmware/intel,stratix10-svc.yaml         |  4 +++
>   .../misc/intel,agilex5-soc-fcs-config.yaml    | 32 +++++++++++++++++++
>   MAINTAINERS                                   |  5 +++
>   arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  4 +++
>   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  5 +++
>   5 files changed, 50 insertions(+)
>   create mode 100644 Documentation/devicetree/bindings/misc/intel,agilex5-soc-fcs-config.yaml
> 

Re: [PATCH 1/4] dt-bindings: misc: agilex5-soc-fcs-config: Add binding

[Krzysztof Kozlowski]

On 12/12/2025 12:35, hangsuan.wang@altera.com wrote:
> From: "Wang, Hang Suan" <hangsuan.wang@altera.com>
> 
> Soc/Hardware FPGA crypto services (fcs) by ensuring optimal performance,
> secure isolation, and robust system management. This will allow dedicated
> system resources to communicate with the high-speed FPGA hardware without
> interruption or software overhead.
> 
> This results in faster, more secure, and consistent cryptographic
> operations compared to running the services entirely on the
> general-purpose CPU.
> 

You don't have resources there, so that's not a real device... And above
explanation does not help me at all. Please carefully read slides for
DTS 101 talk and writing bindings doc.

Best regards,
Krzysztof

Re: [PATCH 2/4] dt-bindings: firmware: stratix10-svc: add fcs-config property

[Krzysztof Kozlowski]

On 12/12/2025 12:35, hangsuan.wang@altera.com wrote:
> From: "Wang, Hang Suan" <hangsuan.wang@altera.com>
> 
> Altera SoC FPGA Crypto Service (fcs) provide hardware crypto features
> through mailbox. Fcs property has to be added to compliance with device
> tree schema fcs bindings and driver.

Last sentence is completely redundant. If you add new devices for some
"compliance" you do it wrong. We don't build hardware for "dt compliance"...

> 
> Signed-off-by: Wang, Hang Suan <hangsuan.wang@altera.com>
> ---
> ---
>  .../devicetree/bindings/firmware/intel,stratix10-svc.yaml     | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> index b42cfa78b28b..c105f8dc4b7d 100644
> --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> @@ -62,6 +62,10 @@ properties:
>      $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
>      description: Optional child node for fpga manager to perform fabric configuration.
>  
> +  fcs-config:
> +    $ref: /schemas/misc/intel,agilex5-soc-fcs-config.yaml
> +    description: Optional child node for fcs Fpga Crypto Service (fcs) to perform SoC Crypto Engine.

You need to wrap according to Linux coding style. Anyway, above schema
is NAKed so is this child.

> +
>  required:
>    - compatible
>    - method


Best regards,
Krzysztof

Re: [PATCH 0/4] Add Device Tree binding and nodes for Agilex5/Agilex SOC FCS configuration.

[Krzysztof Kozlowski]

On 12/12/2025 17:45, Wang, Hang Suan wrote:
> Please disregard this submission.
> Apologizes for inconvenience caused.
> 


I already wasted time on this and then found you don't want to post
it... Recently Altera started sending poor quality patches, so can you
get some internal trainings so you (as a company) follow correct process
and know how to do upstream?

Best regards,
Krzysztof

Re: [PATCH 0/4] Add Device Tree binding and nodes for Agilex5/Agilex SOC FCS configuration.

[Krzysztof Kozlowski]

On 12/12/2025 12:35, hangsuan.wang@altera.com wrote:
> From: "Wang, Hang Suan" <hang.suan.wang@altera.com>
> 
> This patch series introduces necessary Device Tree (DT) support for the
> Soc/Hardware FPGA Crypto Service (fcs) functionality across the Altera
> Agilex SoC families. This feature allows the kernel to identify, interact
> and communicate with the high-speed FPGA hardware without interruption or
> software overhead.
> 
> The series structured as follows:
> Patch 1: Introduces the core YAML schema binding for a generic agilex5,
> soc-fcs-config miscellaneous device.
> Patch 2: Add fcs property to the existing stratix10-svc firmware binding.
> Patch 3&4: Add the fcs nodes to the respective Agilex5 and Agilex DT files.


You cc-ed fake addresses:

Your message to linux-drivers-review@altera.com couldn't be delivered.

Don't do this. Your internal stuff should never be mixed with upstream,
because I do not see reason why we should keep filtering bounces from
your internal email boces.

Best regards,
Krzysztof

Re: [PATCH 0/4] Add Device Tree binding and nodes for Agilex5/Agilex SOC FCS configuration.

[Lee Jones]

On Fri, 12 Dec 2025, hangsuan.wang@altera.com wrote:

> From: "Wang, Hang Suan" <hang.suan.wang@altera.com>
> 
> This patch series introduces necessary Device Tree (DT) support for the
> Soc/Hardware FPGA Crypto Service (fcs) functionality across the Altera
> Agilex SoC families. This feature allows the kernel to identify, interact
> and communicate with the high-speed FPGA hardware without interruption or
> software overhead.
> 
> The series structured as follows:
> Patch 1: Introduces the core YAML schema binding for a generic agilex5,
> soc-fcs-config miscellaneous device.
> Patch 2: Add fcs property to the existing stratix10-svc firmware binding.
> Patch 3&4: Add the fcs nodes to the respective Agilex5 and Agilex DT files.
> 
> ---
> Notes:
> This patch series is applied on socfpga maintainer's tree
> https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19
> 
> ---
> Wang, Hang Suan (4):
>   dt-bindings: misc: agilex5-soc-fcs-config: Add binding
>   dt-bindings: firmware: stratix10-svc: add fcs-config property
>   arm64: dts: socfpga: agilex5: add fcs node
>   arm64: dts: socfpga: agilex: add fcs node
> 
>  .../firmware/intel,stratix10-svc.yaml         |  4 +++
>  .../misc/intel,agilex5-soc-fcs-config.yaml    | 32 +++++++++++++++++++
>  MAINTAINERS                                   |  5 +++
>  arch/arm64/boot/dts/intel/socfpga_agilex.dtsi |  4 +++
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  5 +++

Why am I receiving this?

-- 
Lee Jones [李琼斯]