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Fri, 6 Mar 2026 15:41:30 -0800 From: Nicolin Chen To: , , , CC: , , , , , , , , , , , , Subject: [PATCH v3 0/3] Allow ATS to be always on for certain ATS-capable devices Date: Fri, 6 Mar 2026 15:41:14 -0800 Message-ID: X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDD:EE_|MN0PR12MB6032:EE_ X-MS-Office365-Filtering-Correlation-Id: 311f9635-82e5-40ba-77e4-08de7bd9ebcb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|82310400026|1800799024|13003099007; X-Microsoft-Antispam-Message-Info: /rbEydLWaJu8dORRbWBiozzwudk3MAMmicWswF6cht63Aa6yb7P3LrINfyIjgVRqN8x1/O6pdv/Vk7yv/iJMbQMzbyLB2zMg/Ge/OACRLF/RK5mAsLxoAQMysLozha5p1ZTRi6WgkzbyjRSZyvR6tGyuKsu+c5qLzHoPHWdEfg3gLtydoKS5LetRDxVBJrY0puBEL1Ze0p5IXZpsMo5cmFfFq52B/4Unso31CVgKAnFMixlrJQlcYloDN8cwu/3cyfaTL0ndDpYgnqee/Ct5Pq+n3vVBJzmxRbrt5KEh7roXmscSF032T4bRcjJAI1XPlGPFvvLXD3NQfzX/P4/wA9650Q7M5MJuIKRR6wvJ4mhKHm58T5UtXhtQxihBTA0tXGiQW2btTRzl2zGl1E1ojSlkLI8aArFPBnbUSeIlxnnECbWI3UGi4e/8e7JXokg8kkNjKZICbKHWq6IF/iPomxVxfd6NvuOGeVUjdw6MLJ1G/TeUOFjQVLrIDADPSzaX9WwVn/fKSdHM4kqGyN9xPUiV6uyIidoaq+X8yMk8QczdqDCtu/rWtskKsxnSJ3wmS/TIcSfi2nW/FnBup37Y/ONwmZK2DqXqM9r0jGpzGD6N/TwfRHTGrrrjgqJD/3AZ5aEnhwXTupfMu6fIdbPk8oj2sFLavkIa34ARAWfmVdfCIZhx4L558wjFRqe8t1fQxMR3bi1qYgtQXNrYtEPKrzL0Q36wrrBYWBPqEI8K7I1iZAEXq0NYeqIQsRVPh3OXMGFvAjPDKyhNh93sXYS++w== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(7416014)(82310400026)(1800799024)(13003099007);DIR:OUT;SFP:1101; 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In general, IOMMU driver only enables ATS, when a translation channel is enabled on a PASID, typically for an SVA use case. When a device's RID is IOMMU bypassed and there is no active PASID running SVA use case, ATS is always disabled. However, certain PCIe devices require non-PASID ATS on its RID, even if the RID is IOMMU bypassed. E.g. CXL.cache capability requires ATS to access the physical memory; some pre-CXL NVIDIA GPUs also require the ATS to be always on even when their RIDs are IOMMU bypassed. Provide a helper function to detect CXL.cache capability and scan through a pre-CXL device ID list. As the initial use case, call the helper in ARM SMMUv3 driver and adapt the driver accordingly with a per-device ats_always_on flag. This is on Github: https://github.com/nicolinc/iommufd/commits/pci_ats_always_on-v3/ Changelog v3 * Add Reviewed-by from Jonathan * Update function kdocs of PCI APIs * Simplify boolean return/variable computations v2 * s/non-CXL/pre-CXL * Rebase on v7.0-rc1 * Update inline comments and commit message * Add WARN_ON back at !ptr in arm_smmu_clear_cd() * Add NVIDIA CX10 Family NVlink-C2C to the pre-CXL list * Do not add boolean parameter to arm_smmu_attach_dev_ste() v1 https://lore.kernel.org/all/cover.1768624180.git.nicolinc@nvidia.com/ Nicolin Chen (3): PCI: Allow ATS to be always on for CXL.cache capable devices PCI: Allow ATS to be always on for pre-CXL devices iommu/arm-smmu-v3: Allow ATS to be always on drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/pci/pci.h | 9 +++ include/linux/pci-ats.h | 3 + include/uapi/linux/pci_regs.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 72 ++++++++++++++++++--- drivers/pci/ats.c | 43 ++++++++++++ drivers/pci/quirks.c | 26 ++++++++ 7 files changed, 147 insertions(+), 8 deletions(-) -- 2.43.0