[PATCH 0/5] Support additional AMD EILVT registers

[PATCH 0/5] Support additional AMD EILVT registers

[Naveen N Rao (AMD)]

Future AMD processors will be increasing the number of APIC EILVT 
registers (*). This series adds support for the same along with some 
related cleanups.

(*) https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)


- Naveen


Naveen N Rao (AMD) (5):
  x86/apic: Drop AMD Extended Interrupt LVT macros
  x86/apic: Drop unused AMD EILVT macros
  perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10
  x86/apic: Introduce a variable to track the number of EILVT registers
  x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  9 +--------
 arch/x86/events/amd/ibs.c      | 10 +++++-----
 arch/x86/kernel/apic/apic.c    | 33 +++++++++++++++++++++++++--------
 arch/x86/kernel/cpu/mce/amd.c  |  6 +++---
 5 files changed, 36 insertions(+), 24 deletions(-)


base-commit: cf112712c193e837225d740ec3e139774f2496f2
-- 
2.53.0

[PATCH 1/5] x86/apic: Drop AMD Extended Interrupt LVT macros

[Naveen N Rao (AMD)]

AMD defines Extended Interrupt Local Vector Table (EILVT) registers to
allow for additional interrupt sources. While the APIC registers for
those are unique to AMD, the format of those registers follows the
standard LVT registers. Drop EILVT-specific macros in favor of the
standard APIC LVT macros.

No functional change.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/include/asm/apicdef.h |  5 -----
 arch/x86/events/amd/ibs.c      |  6 +++---
 arch/x86/kernel/apic/apic.c    | 12 ++++++------
 arch/x86/kernel/cpu/mce/amd.c  |  6 +++---
 4 files changed, 12 insertions(+), 17 deletions(-)

diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index be39a543fbe5..f6d821656b02 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -142,11 +142,6 @@
 #define		APIC_EILVT_NR_AMD_10H	4
 #define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
 #define		APIC_EILVT_LVTOFF(x)	(((x) >> 4) & 0xF)
-#define		APIC_EILVT_MSG_FIX	0x0
-#define		APIC_EILVT_MSG_SMI	0x2
-#define		APIC_EILVT_MSG_NMI	0x4
-#define		APIC_EILVT_MSG_EXT	0x7
-#define		APIC_EILVT_MASKED	(1 << 16)
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define APIC_BASE_MSR		0x800
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index eeb607b84dda..e0bd5051db2a 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -1748,7 +1748,7 @@ EXPORT_SYMBOL(get_ibs_caps);
 
 static inline int get_eilvt(int offset)
 {
-	return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
+	return !setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 1);
 }
 
 static inline int put_eilvt(int offset)
@@ -1897,7 +1897,7 @@ static void setup_APIC_ibs(void)
 	if (offset < 0)
 		goto failed;
 
-	if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
+	if (!setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 0))
 		return;
 failed:
 	pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
@@ -1910,7 +1910,7 @@ static void clear_APIC_ibs(void)
 
 	offset = get_ibs_lvt_offset();
 	if (offset >= 0)
-		setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
+		setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_FIXED, 1);
 }
 
 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 0c8970c4c3e3..639904911444 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -332,7 +332,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  * Since the offsets must be consistent for all cores, we keep track
  * of the LVT offsets in software and reserve the offset for the same
  * vector also to be used on other cores. An offset is freed by
- * setting the entry to APIC_EILVT_MASKED.
+ * setting the entry to APIC_LVT_MASKED.
  *
  * If the BIOS is right, there should be no conflicts. Otherwise a
  * "[Firmware Bug]: ..." error message is generated. However, if
@@ -344,9 +344,9 @@ static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 {
-	return (old & APIC_EILVT_MASKED)
-		|| (new == APIC_EILVT_MASKED)
-		|| ((new & ~APIC_EILVT_MASKED) == old);
+	return (old & APIC_LVT_MASKED)
+		|| (new == APIC_LVT_MASKED)
+		|| ((new & ~APIC_LVT_MASKED) == old);
 }
 
 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
@@ -358,13 +358,13 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
 
 	rsvd = atomic_read(&eilvt_offsets[offset]);
 	do {
-		vector = rsvd & ~APIC_EILVT_MASKED;	/* 0: unassigned */
+		vector = rsvd & ~APIC_LVT_MASKED;	/* 0: unassigned */
 		if (vector && !eilvt_entry_is_changeable(vector, new))
 			/* may not change if vectors are different */
 			return rsvd;
 	} while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
 
-	rsvd = new & ~APIC_EILVT_MASKED;
+	rsvd = new & ~APIC_LVT_MASKED;
 	if (rsvd && rsvd != vector)
 		pr_info("LVT offset %d assigned for vector 0x%02x\n",
 			offset, rsvd);
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 146f4207a863..c82266cbd9f6 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -523,7 +523,7 @@ static void mce_threshold_block_init(struct threshold_block *b, int offset)
 static int setup_APIC_mce_threshold(int reserved, int new)
 {
 	if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
-					      APIC_EILVT_MSG_FIX, 0))
+					      APIC_DELIVERY_MODE_FIXED, 0))
 		return new;
 
 	return reserved;
@@ -706,11 +706,11 @@ static void smca_enable_interrupt_vectors(void)
 		return;
 
 	offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12;
-	if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0))
+	if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
 		data->thr_intr_en = 1;
 
 	offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4;
-	if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0))
+	if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
 		data->dfr_intr_en = 1;
 }
 
-- 
2.53.0

[PATCH 2/5] x86/apic: Drop unused AMD EILVT macros

[Naveen N Rao (AMD)]

APIC_EILVT_NR_AMD_K8 and APIC_EILVT_LVTOFF are both unused. Drop them.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/include/asm/apicdef.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index f6d821656b02..bc125c4429dc 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -138,10 +138,8 @@
 #define APIC_SEOI	0x420
 #define APIC_IER	0x480
 #define APIC_EILVTn(n)	(0x500 + 0x10 * n)
-#define		APIC_EILVT_NR_AMD_K8	1	/* # of extended interrupts */
 #define		APIC_EILVT_NR_AMD_10H	4
 #define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
-#define		APIC_EILVT_LVTOFF(x)	(((x) >> 4) & 0xF)
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define APIC_BASE_MSR		0x800
-- 
2.53.0

[PATCH 3/5] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10

[Naveen N Rao (AMD)]

For AMD family 0x10, EILVT offsets are not assigned by BIOS and is
instead assigned by picking the next available EILVT offset.  Use the
maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than
an arbitrary maximum EILVT count when looking for the next available
EILVT offset.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/events/amd/ibs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index e0bd5051db2a..61d14cbdda49 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -1838,13 +1838,13 @@ static void force_ibs_eilvt_setup(void)
 
 	preempt_disable();
 	/* find the next free available EILVT entry, skip offset 0 */
-	for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
+	for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) {
 		if (get_eilvt(offset))
 			break;
 	}
 	preempt_enable();
 
-	if (offset == APIC_EILVT_NR_MAX) {
+	if (offset == APIC_EILVT_NR_AMD_10H) {
 		pr_debug("No EILVT entry available\n");
 		return;
 	}
-- 
2.53.0

[PATCH 4/5] x86/apic: Introduce a variable to track the number of EILVT registers

[Naveen N Rao (AMD)]

Future AMD processors will be increasing the number of EILVT registers.
Rather than hardcoding the maximum EILVT register count and using that
everywhere, introduce a variable to track the EILVT register count.

The number of EILVT registers is exposed through the extended APIC
Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the
count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if
the count is not available.

Export the new variable for KVM since it needs this for supporting
extended APIC register space on AMD.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
http://lore.kernel.org/r/20260204074452.55453-3-manali.shukla@amd.com as 
a related series adding support for KVM and needing access to the EILVT 
register count.

- Naveen


 arch/x86/include/asm/apic.h    |  2 ++
 arch/x86/include/asm/apicdef.h |  1 +
 arch/x86/kernel/apic/apic.c    | 14 ++++++++++++++
 3 files changed, 17 insertions(+)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 9cd493d467d4..8b03c7a14706 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -74,6 +74,8 @@ enum apic_intr_mode_id {
 	APIC_SYMMETRIC_IO_NO_ROUTING
 };
 
+extern unsigned int apic_eilvt_count;
+
 /*
  * With 82489DX we can't rely on apic feature bit
  * retrieved via cpuid but still have to deal with
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index bc125c4429dc..ba7657e75ad1 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -134,6 +134,7 @@
 #define		APIC_TDR_DIV_64		0x9
 #define		APIC_TDR_DIV_128	0xA
 #define	APIC_EFEAT	0x400
+#define		APIC_EFEAT_XLC(x)	(((x) >> 16) & 0xff)
 #define	APIC_ECTRL	0x410
 #define APIC_SEOI	0x420
 #define APIC_IER	0x480
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 639904911444..748e09c5b322 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -341,6 +341,8 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  */
 
 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
+unsigned int apic_eilvt_count __ro_after_init;
+EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count);
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 {
@@ -409,6 +411,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
 }
 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
 
+static __init void init_eilvt(void)
+{
+	if (cpu_feature_enabled(X86_FEATURE_EXTAPIC))
+		apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT));
+
+	if (!apic_eilvt_count)
+		apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
+}
+
 /*
  * Program the next event, relative to now
  */
@@ -1644,6 +1655,9 @@ static void setup_local_APIC(void)
 	if (!cpu)
 		cmci_recheck();
 #endif
+
+	if (!apic_eilvt_count)
+		init_eilvt();
 }
 
 static void end_local_APIC_setup(void)
-- 
2.53.0

[PATCH 5/5] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count

[Naveen N Rao (AMD)]

Switch to using apic_eilvt_count as the maximum EILVT register count.
Since this value is no longer a compile-time constant, update
eilvt_offsets to be dynamically allocated. But do so during init instead
of in reserve_eilvt_offset() since the latter is called with preemption
disabled.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/include/asm/apicdef.h | 1 -
 arch/x86/kernel/apic/apic.c    | 7 +++++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index ba7657e75ad1..32a242ae0455 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -140,7 +140,6 @@
 #define APIC_IER	0x480
 #define APIC_EILVTn(n)	(0x500 + 0x10 * n)
 #define		APIC_EILVT_NR_AMD_10H	4
-#define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define APIC_BASE_MSR		0x800
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 748e09c5b322..c4dfd7e93fe4 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -340,7 +340,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  * necessarily a BIOS bug.
  */
 
-static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
+static atomic_t *eilvt_offsets;
 unsigned int apic_eilvt_count __ro_after_init;
 EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count);
 
@@ -355,7 +355,7 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
 {
 	unsigned int rsvd, vector;
 
-	if (offset >= APIC_EILVT_NR_MAX)
+	if (!eilvt_offsets || offset >= apic_eilvt_count)
 		return ~0;
 
 	rsvd = atomic_read(&eilvt_offsets[offset]);
@@ -418,6 +418,9 @@ static __init void init_eilvt(void)
 
 	if (!apic_eilvt_count)
 		apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
+
+	if (!eilvt_offsets)
+		eilvt_offsets = kzalloc_objs(atomic_t, apic_eilvt_count);
 }
 
 /*
-- 
2.53.0

[tip: x86/cleanups] x86/apic: Drop AMD Extended Interrupt LVT macros

[tip-bot2 for Naveen N Rao (AMD)]

The following commit has been merged into the x86/cleanups branch of tip:

Commit-ID:     5635c8bfd3ab0757c5461d2165f6b284862826bf
Gitweb:        https://git.kernel.org/tip/5635c8bfd3ab0757c5461d2165f6b284862826bf
Author:        Naveen N Rao (AMD) <naveen@kernel.org>
AuthorDate:    Wed, 01 Apr 2026 10:26:32 +05:30
Committer:     Borislav Petkov (AMD) <bp@alien8.de>
CommitterDate: Sat, 04 Apr 2026 00:56:40 +02:00

x86/apic: Drop AMD Extended Interrupt LVT macros

AMD defines Extended Interrupt Local Vector Table (EILVT) registers to allow
for additional interrupt sources. While the APIC registers for those are
unique to AMD, the format of those registers follows the standard LVT
registers. Drop EILVT-specific macros in favor of the standard APIC
LVT macros.

Drop unused APIC_EILVT_NR_AMD_K8 and APIC_EILVT_LVTOFF while at it.

No functional change.

  [ bp: Merge the two cleanup patches into one. ]

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Tested-by: Manali Shukla <manali.shukla@amd.com>
Link: https://patch.msgid.link/b98d69037c0102d2ccd082a941888a689cd214c9.1775019269.git.naveen@kernel.org
---
 arch/x86/events/amd/ibs.c      |  6 +++---
 arch/x86/include/asm/apicdef.h |  7 -------
 arch/x86/kernel/apic/apic.c    | 12 ++++++------
 arch/x86/kernel/cpu/mce/amd.c  |  6 +++---
 4 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index aca89f2..f3a16eb 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -1545,7 +1545,7 @@ EXPORT_SYMBOL(get_ibs_caps);
 
 static inline int get_eilvt(int offset)
 {
-	return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
+	return !setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 1);
 }
 
 static inline int put_eilvt(int offset)
@@ -1694,7 +1694,7 @@ static void setup_APIC_ibs(void)
 	if (offset < 0)
 		goto failed;
 
-	if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
+	if (!setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_NMI, 0))
 		return;
 failed:
 	pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
@@ -1707,7 +1707,7 @@ static void clear_APIC_ibs(void)
 
 	offset = get_ibs_lvt_offset();
 	if (offset >= 0)
-		setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
+		setup_APIC_eilvt(offset, 0, APIC_DELIVERY_MODE_FIXED, 1);
 }
 
 static int x86_pmu_amd_ibs_starting_cpu(unsigned int cpu)
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index be39a54..bc125c4 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -138,15 +138,8 @@
 #define APIC_SEOI	0x420
 #define APIC_IER	0x480
 #define APIC_EILVTn(n)	(0x500 + 0x10 * n)
-#define		APIC_EILVT_NR_AMD_K8	1	/* # of extended interrupts */
 #define		APIC_EILVT_NR_AMD_10H	4
 #define		APIC_EILVT_NR_MAX	APIC_EILVT_NR_AMD_10H
-#define		APIC_EILVT_LVTOFF(x)	(((x) >> 4) & 0xF)
-#define		APIC_EILVT_MSG_FIX	0x0
-#define		APIC_EILVT_MSG_SMI	0x2
-#define		APIC_EILVT_MSG_NMI	0x4
-#define		APIC_EILVT_MSG_EXT	0x7
-#define		APIC_EILVT_MASKED	(1 << 16)
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 #define APIC_BASE_MSR		0x800
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index d93f87f..eb2d825 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -332,7 +332,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
  * Since the offsets must be consistent for all cores, we keep track
  * of the LVT offsets in software and reserve the offset for the same
  * vector also to be used on other cores. An offset is freed by
- * setting the entry to APIC_EILVT_MASKED.
+ * setting the entry to APIC_LVT_MASKED.
  *
  * If the BIOS is right, there should be no conflicts. Otherwise a
  * "[Firmware Bug]: ..." error message is generated. However, if
@@ -344,9 +344,9 @@ static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
 
 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
 {
-	return (old & APIC_EILVT_MASKED)
-		|| (new == APIC_EILVT_MASKED)
-		|| ((new & ~APIC_EILVT_MASKED) == old);
+	return (old & APIC_LVT_MASKED)
+		|| (new == APIC_LVT_MASKED)
+		|| ((new & ~APIC_LVT_MASKED) == old);
 }
 
 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
@@ -358,13 +358,13 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
 
 	rsvd = atomic_read(&eilvt_offsets[offset]);
 	do {
-		vector = rsvd & ~APIC_EILVT_MASKED;	/* 0: unassigned */
+		vector = rsvd & ~APIC_LVT_MASKED;	/* 0: unassigned */
 		if (vector && !eilvt_entry_is_changeable(vector, new))
 			/* may not change if vectors are different */
 			return rsvd;
 	} while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
 
-	rsvd = new & ~APIC_EILVT_MASKED;
+	rsvd = new & ~APIC_LVT_MASKED;
 	if (rsvd && rsvd != vector)
 		pr_info("LVT offset %d assigned for vector 0x%02x\n",
 			offset, rsvd);
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index da13c1e..3a689d3 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -521,7 +521,7 @@ static void mce_threshold_block_init(struct threshold_block *b, int offset)
 static int setup_APIC_mce_threshold(int reserved, int new)
 {
 	if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
-					      APIC_EILVT_MSG_FIX, 0))
+					      APIC_DELIVERY_MODE_FIXED, 0))
 		return new;
 
 	return reserved;
@@ -704,11 +704,11 @@ static void smca_enable_interrupt_vectors(void)
 		return;
 
 	offset = (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12;
-	if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_EILVT_MSG_FIX, 0))
+	if (!setup_APIC_eilvt(offset, THRESHOLD_APIC_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
 		data->thr_intr_en = 1;
 
 	offset = (mca_intr_cfg & MASK_DEF_LVTOFF) >> 4;
-	if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_EILVT_MSG_FIX, 0))
+	if (!setup_APIC_eilvt(offset, DEFERRED_ERROR_VECTOR, APIC_DELIVERY_MODE_FIXED, 0))
 		data->dfr_intr_en = 1;
 }