From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D106264A9D for ; Wed, 1 Apr 2026 04:57:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019459; cv=none; b=FrcXQwoBcP10BnXX7+1B5byaLW4g2XeaS+VVLc8ExGhqimVfDXwWxfFx8m6Pveya19Yjg+0polUL+eIOgZau0BtX4XmZmp9dgc6PE/f3zIRSjHeNdoH6jggQfmKrsIJtx2gRnM24ezUGCCBMbmwfXszrQSYs4kv7DExtMtJt/Io= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775019459; c=relaxed/simple; bh=GJUMmYS7Mz5vWWqcb6pwH34PBiBhYRe2Kc5H+UMn0Uw=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=bL0Qo9erLp1ORNatq5y1L0SsDnt3Ktiqk0nFY+L86JKIHE/qAMO3mFIZCTocrpPjwQ65LKZPY50+axXatLKfHBGnvT5xLdZ4nelEBcw0UDFhKqJpsQ3YZiYVdX3cKMMxFtvOYaM9T11DyUqbPOwoGCRPVUVwxbpXt7e7ENYmjy0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KKT2TNas; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KKT2TNas" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08AE3C4CEF7; Wed, 1 Apr 2026 04:57:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775019458; bh=GJUMmYS7Mz5vWWqcb6pwH34PBiBhYRe2Kc5H+UMn0Uw=; h=From:To:Cc:Subject:Date:From; b=KKT2TNasoKqs0hqnNbosqmxYohQ5Kha3S8W+G9140rt/rmYnMMub8Y6STyugHBLkV rD4Q+t4BRyabffEP9lINqHgHcs0E07rwcKLCfQiA5+LdKiWF5FvEuIm03hz1xpRwR/ q4PM6EOUBKn5VZ0mdB1qtlOGaAe+S+nsoI5+DvJ99w+cWe+tTy06y6Mgn85vHP6qaN MZ/6ULub4Fsphl3IgnMou0llNpFOUi8ESmjcqYtfYBQoCIxNR5sRR+wrGNzhP7YDJQ zKh3aORFWQL4tsuI3BxpPmsxbdyVOH16zS3xPi0iWqHWlyOxkVHQZ9x8xLo9Bvs/QL SnhAGSrzNILcA== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao Subject: [PATCH 0/5] Support additional AMD EILVT registers Date: Wed, 1 Apr 2026 10:26:31 +0530 Message-ID: X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Future AMD processors will be increasing the number of APIC EILVT registers (*). This series adds support for the same along with some related cleanups. (*) https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB) - Naveen Naveen N Rao (AMD) (5): x86/apic: Drop AMD Extended Interrupt LVT macros x86/apic: Drop unused AMD EILVT macros perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 x86/apic: Introduce a variable to track the number of EILVT registers x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 9 +-------- arch/x86/events/amd/ibs.c | 10 +++++----- arch/x86/kernel/apic/apic.c | 33 +++++++++++++++++++++++++-------- arch/x86/kernel/cpu/mce/amd.c | 6 +++--- 5 files changed, 36 insertions(+), 24 deletions(-) base-commit: cf112712c193e837225d740ec3e139774f2496f2 -- 2.53.0