From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B47513AB49A for ; Tue, 12 May 2026 14:26:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595978; cv=none; b=X1KhYdxd0sKZ0hezxNbTmzxa2QswtoxExJ8mTghBnWiW5qhWNlItKddz4zdZZLNb/67ITzmHnAyJUKKp7d0OljsAgS4dyf8CQyDArT1lNxdRZgJMdGnhfB3RRc24PBJ9MSq2xCO52q3JGxcpoJ20iuJUE2IGsKFhQWiemuuR0RU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595978; c=relaxed/simple; bh=VrFev0l8G0suMJR7jMHfFWMrHfzjZHSiR8CJkrfAq9E=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=VaTdFyu0Ou6bgdXNoDCDRmZezGGiWFRAOrIl2zu6RZMyGDkFmFcUQKwhQPeF0pIX0SzhqPg1Xv+UyYZUq8JdOoYAvpUKLLxi7KIWvoSOC9jeVX0e2BO9I7OFbXqRp1x6ZrcPnF3t7WalFoBSf2hqCWRHu/polGSlGLXJdfV+d68= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nmncpgfo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nmncpgfo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17AB9C2BCB0; Tue, 12 May 2026 14:26:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778595978; bh=VrFev0l8G0suMJR7jMHfFWMrHfzjZHSiR8CJkrfAq9E=; h=From:To:Cc:Subject:Date:From; b=nmncpgfoukKi2UxjRiLfbppPx9IQvqPu4s00RSlBHp0s2V65y7ctEMyssOoz0S52u m8fRasYqIv7t2GZwoXd+oQCRoOYryfIdwoK383bQjY7nFD9d58Z3gPnhCyR7kA7XTH L4z7IiyT3LPK+oRjbDwuYWvE5I5Kdu3BdnnJao0fMHPPDQg/DykFBUVkJu+XfOXNtR SosPte4zoufjPOEdlc/guHOBKgpkTEqycU8qo1HOT99znhqTex/Q5MSRwBOkdDWXxe CpSUAla+Q9t9Ll/XS7nb2/lbdEHvAFR5olOUF+Xpb/m5vHFdTOjL8/EBDVS0PDlsnZ kkq4M7PC7cEeA== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , Subject: [PATCH v2 0/3] Support additional AMD EILVT registers Date: Tue, 12 May 2026 19:49:14 +0530 Message-ID: X-Mailer: git-send-email 2.54.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This is v2 of the series posted at: http://lore.kernel.org/r/cover.1775019269.git.naveen@kernel.org Changes since v1: - Drop the first two patches that were merged - Call init_eilvt() from apic_bsp_setup(), rather than setup_local_APIC() so as not to call an __init function from a non-init function. (Kernel 0-day bot) - Initialize eilvt count to APIC_EILVT_NR_AMD_10H and allocate eilvt_offsets array only on AMD processors. Manali, I am retaining your Tested-by: tag since the changes are minimal, but please reply here if you have concerns with the changes. -- Future AMD processors will be increasing the number of APIC EILVT registers (*). This series adds support for the same along with some related cleanups. (*) https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB) - Naveen Naveen N Rao (AMD) (3): perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 x86/apic: Introduce a variable to track the number of EILVT registers x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 2 +- arch/x86/events/amd/ibs.c | 4 ++-- arch/x86/kernel/apic/apic.c | 19 +++++++++++++++++-- 4 files changed, 22 insertions(+), 5 deletions(-) base-commit: 70e7aca9f7ff4d1bee94c5b04973c3dbca1dba00 -- 2.54.0