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[109.193.28.127]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-490e2c7ea21sm42585795e9.1.2026.06.11.00.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 00:26:36 -0700 (PDT) From: Marek Czernohous X-Google-Original-From: Marek Czernohous To: Lyude Paul , Danilo Krummrich Cc: dri-devel@lists.freedesktop.org, nouveau@lists.freedesktop.org, linux-kernel@vger.kernel.org, Fab Stz Subject: [PATCH v2 0/2] drm/nouveau: NVAC (MCP79) MSI rearm + SOR-disable NULL guard Date: Thu, 11 Jun 2026 09:26:32 +0200 Message-ID: X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This is a v2 of the NVAC (MCP79/MCP7A) stability series, narrowed to the two changes that are genuinely stable material and reworked after review plus an independent second-machine test. The original v1 [1] was a three-patch series. Since then it has had a three-week soak on my Apple Mac mini (early 2009, MCP79) and an independent test by Fab Stz on a second machine (iMac9,1 / MCP79, 6.12.90, X11/KDE 6), who confirmed the system is more stable with the series and provided a Tested-by. After an internal review pass: Patch 1 (MSI rearm): NVAC re-arms MSI through the MMIO mirror of PCI config space, which is unreliable on this IGP; a missed re-arm leaves the interrupt line dead and the GPU wedges. v1 switched the whole shared g94_pci_func (ten chipsets); v2 narrows this to a dedicated mcp79 pci func so only the tested chipset (0xac) changes, matching the existing g92 precedent. Patch 2 (SOR disable NULL guard): nv50_sor_atomic_disable() can run with a NULL nv_encoder->crtc under Wayland session teardown / VT switches, and because the deref goes through container_of() the NULL becomes a bogus pointer that faults. v2 restores the guard as drm_WARN_ON_ONCE() and, unlike v1, does not call nvif_outp_release() in the early return (that path is owned by the commit_tail release loop; the v1 form could release twice and detach the OR before the disable flush). The v1 patch 3 (HPD link-check retry) is intentionally dropped from this series: it is a behavioral workaround that sleeps under mode_config.mutex, not an obviously-correct fix, so it does not meet the stable bar. I will revisit it separately if it is still needed. Both patches carry Fixes: and Cc: stable tags. Per-patch v1 -> v2 changelogs are under the --- in each patch. Disclosure: this work was done with assistance from an AI coding assistant (Anthropic's Claude, Opus 4.7 and 4.8); the analysis and conclusions are mine and have been verified on hardware. Each patch also carries an Assisted-by trailer to that effect. [1] https://lore.kernel.org/nouveau/20260409172126.115441-1-marek@czernohous.de/ Marek Czernohous (2): drm/nouveau/pci: use config-space MSI rearm on MCP79/MCP7A (NVAC) drm/nouveau/kms: guard NULL crtc in nv50_sor_atomic_disable() drivers/gpu/drm/nouveau/dispnv50/disp.c | 16 ++++++++- .../gpu/drm/nouveau/include/nvkm/subdev/pci.h | 2 ++ .../gpu/drm/nouveau/nvkm/engine/device/base.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/pci/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/subdev/pci/mcp79.c | 33 +++++++++++++++++++ 5 files changed, 52 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/nvkm/subdev/pci/mcp79.c -- 2.53.0