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Thu, 11 Jun 2026 13:02:53 -0700 (PDT) Received: from geday ([2804:7f2:800b:f09::dead:c001]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8d30105fd9csm3244376d6.10.2026.06.11.13.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jun 2026 13:02:53 -0700 (PDT) Date: Thu, 11 Jun 2026 17:02:42 -0300 From: Geraldo Nascimento To: Shawn Lin , Dragan Simic Cc: linux-rockchip@lists.infradead.org, Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Geraldo Nascimento Subject: [PATCH v6 0/3] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Dragan Simic already had warned me of potential issues with 5.0 GT/s speed operation in Rockchip PCIe. However, in recent interactions with Shawn Lin from Rockchip it came to my attention there's grave danger in the unknown errata regarding 5.0 GT/s operational speed of their PCIe core, including data loss. Drop all code related to 5.0 GT/s operational speed from this driver. Endpoint Mode driver was not tested. --- Changes in v6: - Squashed patches 3 & 4 together as suggested by Mani - More formal warning message as suggested by Dragan - Set the 2.5 GT/s bit regardless of if link-speed is set to 2 - Link to v5: https://lore.kernel.org/all/cover.1772239598.git.geraldogabriel@gmail.com/T/ Changes in v5: - Changed commit order to not break builds and adjusted copy pasted commit message. (thanks Charalampos!) - Reintroduced behavior to force 2.5 GT/s in case there's something non-default in the DT. (thanks Dragan!) - Link to v4: https://lore.kernel.org/linux-rockchip/cover.1772169998.git.geraldogabriel@gmail.com/T/ Changes in v4: - Incorporate suggestion by Bjorn and refined by Dragan to drop the "catastrophic" code - Link to v3: https://lore.kernel.org/linux-rockchip/cover.1772057799.git.geraldogabriel@gmail.com/T/ Changes in v3: - Clarify warning message even though Rockchip won't disclose details - Drop DT changes as they were applied as subset by Heiko - Link to v2: https://lore.kernel.org/all/cover.1763415705.git.geraldogabriel@gmail.com/T/ Changes in v2: - hard limit to 2.5 GT/s, not just warn - add Reported-by: and Reviewed-by: Dragan Simic - remove redundant declaration of max-link-speed from helios64 dts - fix Link: of helios64 patch - simplify RC mode comment - Link to v1: https://lore.kernel.org/all/aRhR79u5BPtRRFw3@geday/T/ --- Geraldo Nascimento (3): PCI: rockchip-ep: do not attempt 5.0 GT/s retraining PCI: rockchip-host: do not attempt 5.0 GT/s retraining PCI: rockchip: drive at 2.5 GT/s, error other speeds drivers/pci/controller/pcie-rockchip-ep.c | 13 ------------- drivers/pci/controller/pcie-rockchip-host.c | 20 -------------------- drivers/pci/controller/pcie-rockchip.c | 16 +++++++++------- drivers/pci/controller/pcie-rockchip.h | 3 --- 4 files changed, 9 insertions(+), 43 deletions(-) -- 2.54.0