From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFA54343899 for ; Sat, 13 Jun 2026 08:06:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781337994; cv=none; b=Hwou+3553gQ5Rg3+qDtkqEA4Hk83VznS+BLOVY3gDA3UX2qrqpFS2IYottKOOJ6jZLt5kwoo/wN9kkHjb1Xe08iMXc0q0ShEXitCo0/y0ZOuZwrKEyb/omcQshYdcmoX1UvE9W8d4slntsAzHJIb5OyKoHr2SlXUNSbEqy4MHuE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1781337994; c=relaxed/simple; bh=0r7bXI3qYC81fQCwqGeKscHmddXi58n2FLeXZ/M3t0k=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=lHuG8DgUM+yD6h+qBjgp4sv8yugBXxflGpmxs4TODMzdzjt8YikSfTRITIAVXFjyBJah0iIkz3cCdcGvKxI1bCCeb1C+mwjO5eNXwxs60Xf1m7TeDtDhG/zVj+ksMsM1lAyeAs028C8GvdjZgcqHMiNoJWuMNYxJYa3/Xp5fVeI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jRxsoEOm; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jRxsoEOm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1781337993; x=1812873993; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=0r7bXI3qYC81fQCwqGeKscHmddXi58n2FLeXZ/M3t0k=; b=jRxsoEOmlw/w6Df1RmZYfcWl/FX1CaUyxWKXwFGVd9rJsmRfDeKFV0xZ RiNGLvw/HAUCv5NxaFln0HGmGFMaVPy/Q3pg3lwx51bpd5IqtQHfwbO+F K481w26Pyq3ueCdJjuPm5lCtig+3hpGYhUNEydh16QV+VyH1AoP9uhMC2 DHHlKR/D7RpN88yuUhVT90G3us7jQPJiWcw2H7g35HXNGYWfGXUpL5ixN N5J+MpgA6qW1TiybYrB2uq0kuZGmYy61lgn0u9/UIAO2PRspwEU7Fyy2u ShPcP6ZI1Mg6kI8d8Ny6rsP1TpIz+hOEfWFcSZUkwd9a71xalPOBHN0Nb A==; X-CSE-ConnectionGUID: KOXRnl1jQm6G1M9oNQAHyA== X-CSE-MsgGUID: KckO8OxsQ82OBKG+J93QBQ== X-IronPort-AV: E=McAfee;i="6800,10657,11815"; a="82222855" X-IronPort-AV: E=Sophos;i="6.24,202,1774335600"; d="scan'208";a="82222855" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jun 2026 01:06:32 -0700 X-CSE-ConnectionGUID: CQBe5SQ2R26u1tv+yOfI8w== X-CSE-MsgGUID: 55/JK0+hRvmiYP8vyOhl7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,202,1774335600"; d="scan'208";a="245900361" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by orviesa006.jf.intel.com with ESMTP; 13 Jun 2026 01:06:27 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, tglx@kernel.org, bp@alien8.de, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, dave.martin@arm.com, james.morse@arm.com, fenghuay@nvidia.com, babu.moger@amd.com, anil.keshavamurthy@broadcom.com Subject: [PATCH v4 0/6] Introduce MMIO-based CMT access for Enhanced RDT Date: Sat, 13 Jun 2026 15:56:39 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Intel Enhanced Resource Director Technology (ERDT) extends the existing RDT framework with two major capabilities: 1. MMIO-based access to monitoring and allocation registers, replacing the legacy MSR-based interface. 2. Region-aware RDT for fine-grained control over different tiers of memory (e.g., CXL.mem, DDR). This is described in the Intel RDT Architecture Specification: https://cdrdv2-public.intel.com/789566/356688-intel-rdt-arch-spec.pdf This patch set focuses on the first part: enabling MMIO-based access for Cache Monitoring Technology (CMT), while CAT/MBM/MBA are still using MSR. The platform advertises the MMIO register layout through the ACPI ERDT (Enhanced Resource Director Technology) table, which contains sub-tables describing per-domain register regions for monitoring and allocation. With ERDT, L3 cache occupancy counters are read via MMIO rather than MSR, allowing the reads to be performed from any CPU without requiring cross-CPU IPIs. This series parses the relevant ACPI sub-tables (RMDD, CMRC), prepares the resctrl monitor infrastructure for MMIO-based reads, and adds initial support for reading L3 occupancy via the CMRC interface. kselftest of CMT and L3_CAT has passed with minor adjustment at https://lore.kernel.org/lkml/20260523101715.3964456-1-yu.c.chen@intel.com/. Changes from V3 to V4: - Remove the redundant table length check in subtbl_valid() (Thomas Gleixner) - Reuse subtbl_valid() for all the table iteration (Thomas Gleixner) - Refine the commit log of [PATCH 5/6] to state that this change is a preparation for [PATCH 6/6] rather than fixing an existing issue (Thomas Gleixner, Reinette Chatre, Tony Luck) - Fix if CACD lists all CPUs in the LLC domain (sashiko) - Deal with a corner case that if there is no valid RMDD tables, the erdt_enabled_flag should remain false.(sashiko) - Add Thomas's Reviewed-by and Hongyu's Tested-by. Changes from V2 to V3: - Wrap __resctrl_arch_late_init() to avoid the goto logic. (Thomas Gleixner) - Make the variables in struct erdt_domain_info tabular format (Thomas Gleixner) - Remove tail comments (Thomas Gleixner) - Make the name of erdt_enabled() and variable in it consistent and comprehensible. (Thomas Gleixner) - Use topo_lookup_cpuid() to search the CPU id according to the x2apic id (Thomas Gleixner) - Fix kernel doc comment format (Thomas Gleixner) - Use brackets for multiple lines "if" case. (Thomas Gleixner) - Let the parameter for cacd_init() to fully utilize 100 characters. (Thomas Gleixner) - Variables are reordered in reverse fir-tree.(Thomas Gleixner) - Added a named constant and use it in the rmdd->flags check. (Thomas Gleixner) - Introduce helper functions to make the code readable when iterating the RMDD tables. (Thomas Gleixner) - Make the macros tabular format. (Thomas Gleixner) Changes from V1 to V2: - Add #include to follow the "include-what-you-use" best practice (Tony Luck) - Fix 3 issues reported by: https://sashiko.dev/#/patchset/cover.1779872016.git.yu.c.chen%40intel.com Remove the variable of cacd in struct erdt_domain_info as it will never be used after initialization. Invoke erdt_exit() to avoid resource leak if rdt_alloc_capable and rdt_mon_capable are both false. Adjust the comments suggested by sashiko. Anil S Keshavamurthy (1): x86/resctrl: Parse ACPI ERDT table and map RMDD domains by L3 cache ID Chen Yu (4): x86/resctrl: Parse ACPI CMRC table x86/resctrl: Rename prev_msr to prev_mon_val x86/resctrl: Refactor the monitor read function x86/resctrl: Add support for L3 occupancy monitoring via RMID MMIO read Tony Luck (1): fs/resctrl: Do not invoke smp_processor_id() in preemptible context arch/x86/Kconfig | 4 +- arch/x86/include/asm/apic.h | 1 + arch/x86/include/asm/resctrl.h | 4 + arch/x86/kernel/cpu/resctrl/Makefile | 1 + arch/x86/kernel/cpu/resctrl/core.c | 16 +- arch/x86/kernel/cpu/resctrl/erdt.c | 425 +++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 11 +- arch/x86/kernel/cpu/resctrl/monitor.c | 64 ++-- arch/x86/kernel/cpu/topology.c | 2 +- fs/resctrl/monitor.c | 42 ++- 10 files changed, 528 insertions(+), 42 deletions(-) create mode 100644 arch/x86/kernel/cpu/resctrl/erdt.c -- 2.25.1