From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32D92274B4A for ; Wed, 1 Jul 2026 13:54:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782914090; cv=none; b=Hq4RXt5m8MCND4Epg0W/JUkTD4W2VbteuYndILX4og+BYR8RlUBNqTsooDqgl0KJXPMHL36zbYdLGq5IlIaD3r5g7qOSQ2bV1Zqdums0FZLIsH2tYEb0Y1huMs5uFuCXzpEgsHsegascwXWK/SnMVQgWQEgQBHli97UbmNhnEmY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782914090; c=relaxed/simple; bh=OKAMp4NptkkEhwP5irCzYK5R1/48II4C6eA/Eb0BbIg=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=ISVsL2TOLqiUG7GR43bIZkKLwzcgi4coyHRkvic1D8L2PCSwHDn3Sx1z/yPiJcnVmMCQR3mmqdhM6mVVgeAQpisM1UBRngeJnoZXndHGDNXLRP9PXQo0+EIiHJi1S+JhfU5sME6cdEk6AUL2rai86Awf0U/fCTGLN7qb/JDpVUM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DXDOt1Ck; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DXDOt1Ck" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1782914089; x=1814450089; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=OKAMp4NptkkEhwP5irCzYK5R1/48II4C6eA/Eb0BbIg=; b=DXDOt1CkUAD7AHtazjK41ITSeT5FpiYpE8712e89Sz2tz6ZvEiRxxfnm mSjpgr3ynYDm8GSM8qc/rKmEkAvJDrsB2FpF0PWvgcb785hR8CWSdXJpE uaaW8w9t0Ick3antxXss6ZGWiFZJDvwSq4jMJCsSvznfVXEci7K+1K7jg 5ZDPlVIE9qkU+n3S8I6anPvAcyIunDIs4VtSH856WmY3ycmLGUBs4tQTC 0lasK9h6LKthn+vT0fE7Kh80/HudeZ67cgwXHxSg8gazu3HC6uwPK9hUu e8HhLNXAJpLd+K04w0GyweZNVUH+nNtL8q/0QlsESwIb9mJmAokYw7vdI g==; X-CSE-ConnectionGUID: VdkG/WTwT3mruqhRMoW5vw== X-CSE-MsgGUID: cHrFygJLS4udVwySoG81xw== X-IronPort-AV: E=McAfee;i="6800,10657,11833"; a="95149498" X-IronPort-AV: E=Sophos;i="6.25,141,1779174000"; d="scan'208";a="95149498" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Jul 2026 06:54:48 -0700 X-CSE-ConnectionGUID: vf/9usAfRHiJFUjek4AEoQ== X-CSE-MsgGUID: NzROHCTySIu3zhy7CUud3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,141,1779174000"; d="scan'208";a="246213533" Received: from chenyu-dev.sh.intel.com ([10.239.62.107]) by fmviesa009.fm.intel.com with ESMTP; 01 Jul 2026 06:54:43 -0700 From: Chen Yu To: tony.luck@intel.com, reinette.chatre@intel.com Cc: x86@kernel.org, linux-kernel@vger.kernel.org, tglx@kernel.org, bp@alien8.de, mingo@redhat.com, dave.hansen@linux.intel.com, hpa@zytor.com, fenghuay@nvidia.com, babu.moger@amd.com, anil.keshavamurthy@broadcom.com, chen.yu@linux.dev, Chen Yu Subject: [PATCH v5 00/10] Introduce MMIO-based CMT access for Enhanced RDT Date: Wed, 1 Jul 2026 21:44:44 +0800 Message-Id: X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit v4: https://lore.kernel.org/lkml/cover.1781332698.git.yu.c.chen@intel.com/ v3: https://lore.kernel.org/lkml/cover.1780710620.git.yu.c.chen@intel.com/ v2: https://lore.kernel.org/lkml/cover.1780587063.git.yu.c.chen@intel.com/ v1: https://lore.kernel.org/lkml/cover.1779872016.git.yu.c.chen@intel.com/ Intel Enhanced Resource Director Technology (ERDT) extends the existing RDT framework with two major capabilities: 1. MMIO-based access to monitoring and allocation registers, replacing the legacy MSR-based interface. 2. Region-aware RDT for fine-grained control over different tiers of memory (e.g., CXL.mem, DDR). This is described in the Intel RDT Architecture Specification: https://cdrdv2-public.intel.com/789566/356688-intel-rdt-arch-spec.pdf This patch set focuses on the first part: enabling MMIO-based access for Cache Monitoring Technology (CMT), while CAT/MBM/MBA are still using MSR. The platform advertises the MMIO register layout through the ACPI ERDT (Enhanced Resource Director Technology) table, which contains sub-tables describing per-domain register regions for monitoring and allocation. With ERDT, L3 cache occupancy counters are read via MMIO rather than MSR, allowing the reads to be performed from any CPU without requiring cross-CPU IPIs. This series parses the relevant ACPI sub-tables (RMDD, CMRC), prepares the resctrl monitor infrastructure for MMIO-based reads, and adds initial support for reading L3 occupancy via the CMRC interface. kselftest of CMT and L3_CAT has passed with minor adjustment at https://lore.kernel.org/lkml/20260523101715.3964456-1-yu.c.chen@intel.com/. V5 has undergone internal Sashiko review. Changes from V4 to V5: There are some major changes since v4: - (biggest change) Eliminate the xarray for runtime lookups; embed struct erdt_domain_info directly in rdt_hw_l3_mon_domain and assign during l3_mon_domain_setup(). - Separate CPUID and ACPI enumeration cleanly. Do not use CPUID feature flags to gate MMIO-based monitoring. Use ACPI table presence (e.g., CMRC table) to determine event enablement. - Use ACPI RMDD's own "Max RMID" field for MMIO access instead of relying on CPUID's max RMID (which applies to MSR). - Enforce the SNC constraint in code rather than burying it behind a comment WARN. Disable mon_capable in rdt_get_l3_mon_config() when ERDT is enabled and snc_nodes_per_l3_cache > 1. - Split non-resctrl changes (topology.c, apic.h) into a separate preparatory patch prefixed with x86/topology. - Move the "depends on X86" to "X86_64" adjustment to a separate patch with explicit justification in its changelog. Misc in V5: - arch_priv is not used to distinguish whether a monitor is MSR-based or ERDT backed, since a unified erdt_cpu_has() is introduced to check whether a specific RDT feature is backed by ERDT and its sub-tables. [PATCH 9/10] - I have removed Thomas's Reviewed-by tag from [PATCH 10/10], as the patch was updated to rely on erdt_cpu_has(). Thanks Tony, Reinette, Thomas, Hongyu for your time to look at this patch set. Changes from V3 to V4: - Remove the redundant table length check in subtbl_valid() (Thomas Gleixner) - Reuse subtbl_valid() for all the table iteration (Thomas Gleixner) - Refine the commit log of [PATCH 5/6] to state that this change is a preparation for [PATCH 6/6] rather than fixing an existing issue (Thomas Gleixner, Reinette Chatre, Tony Luck) - Fix if CACD lists all CPUs in the LLC domain (sashiko) - Deal with a corner case that if there is no valid RMDD tables, the erdt_enabled_flag should remain false.(sashiko) - Add Thomas's Reviewed-by and Hongyu's Tested-by. Changes from V2 to V3: - Wrap __resctrl_arch_late_init() to avoid the goto logic. (Thomas Gleixner) - Make the variables in struct erdt_domain_info tabular format (Thomas Gleixner) - Remove tail comments (Thomas Gleixner) - Make the name of erdt_enabled() and variable in it consistent and comprehensible. (Thomas Gleixner) - Use topo_lookup_cpuid() to search the CPU id according to the x2apic id (Thomas Gleixner) - Fix kernel doc comment format (Thomas Gleixner) - Use brackets for multiple lines "if" case. (Thomas Gleixner) - Let the parameter for cacd_init() to fully utilize 100 characters. (Thomas Gleixner) - Variables are reordered in reverse fir-tree.(Thomas Gleixner) - Added a named constant and use it in the rmdd->flags check. (Thomas Gleixner) - Introduce helper functions to make the code readable when iterating the RMDD tables. (Thomas Gleixner) - Make the macros tabular format. (Thomas Gleixner) Changes from V1 to V2: - Add #include to follow the "include-what-you-use" best practice (Tony Luck) - Fix 3 issues reported by: https://sashiko.dev/#/patchset/cover.1779872016.git.yu.c.chen%40intel.com Remove the variable of cacd in struct erdt_domain_info as it will never be used after initialization. Invoke erdt_exit() to avoid resource leak if rdt_alloc_capable and rdt_mon_capable are both false. Adjust the comments suggested by sashiko. Anil S Keshavamurthy (1): x86/resctrl: Parse ACPI ERDT table and save CACD cpumask for RMDD domains Chen Yu (8): x86/resctrl: Require 64-bit x86 for resctrl support x86/topology: Export topo_lookup_cpuid() for resctrl use x86/resctrl: Attach ACPI ERDT information to L3 mon domain on CPU online x86/resctrl: Parse ACPI CMRC table x86/resctrl: Replace "msr" in monitoring data identifiers x86/resctrl: Refactor the monitor read function x86/resctrl: Introduce helpers to read L3 occupancy via MMIO x86/resctrl: Enable read L3 occupancy via MMIO Tony Luck (1): fs/resctrl: Do not invoke smp_processor_id() in preemptible context arch/x86/Kconfig | 4 +- arch/x86/include/asm/apic.h | 1 + arch/x86/include/asm/resctrl.h | 6 + arch/x86/kernel/cpu/resctrl/Makefile | 1 + arch/x86/kernel/cpu/resctrl/core.c | 64 +++- arch/x86/kernel/cpu/resctrl/erdt.c | 439 +++++++++++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 40 ++- arch/x86/kernel/cpu/resctrl/monitor.c | 82 +++-- arch/x86/kernel/cpu/topology.c | 2 +- fs/resctrl/monitor.c | 48 ++- include/linux/resctrl.h | 1 + 11 files changed, 643 insertions(+), 45 deletions(-) create mode 100644 arch/x86/kernel/cpu/resctrl/erdt.c -- 2.45.2