From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DF9E3803C1 for ; Wed, 1 Jul 2026 04:21:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782879673; cv=none; b=L5oSwrZrxZcxnGXG6MWViVwZBlD+SiMgoz0zfMr/HH0GOhnnGlC8htnCdYjmrA4fJOVJ/DW7DgD0Jl/WBeuXBcCZy+44UVDkgJUDfLg1FQdUgIqkDj3vsCQerojIin+7gObADHo23lEZpf53o5WzQQThUb96OHFEq35TapC4nFc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782879673; c=relaxed/simple; bh=ndidOr7I8IHgvxf1AeP1Ck+0PatfZjEXy4LWSt++W30=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=EFtZQ2FFaWh6pzvXZ06c7W22P9y9MCMRY32Ogc0Lcom7mZjZnmMDdcpTg/xmujUQ+1Y0kWDSoF2X8azcHAv6HjOj2q78wlYM2hKkPyLykxFxVBSkDw33QHcbxMlTuu3YWFONMuEb2RDbrW7OZbtSXgMkoz+KLc/KflvVS4qVppU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=dKtmCoE+; arc=none smtp.client-ip=209.85.214.180 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="dKtmCoE+" Received: by mail-pl1-f180.google.com with SMTP id d9443c01a7336-2ca11143dbbso1063605ad.2 for ; Tue, 30 Jun 2026 21:21:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1782879669; x=1783484469; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=wIXJacBAyEaKz61QqT13AHUcLwATDSXxJV4uZgWwmww=; b=dKtmCoE+cMY+ae/6a2cuOy+r+DPt6J+S4DxJSxhCK/iVk2m5G8zm0VFeoSMS++ijC8 ZikwGoEKOiyIGXH/IwGqj2V3NbknCEcKa93vP8AMlFJfJIzRpw4PF+yRwt5swNe64yCy m8RhGaagOMQX53X3qrgHwEdkmNXf1zbFkYp4UvFI6OerLariet9nHvlCJipDMGvI8O+a Qx/5LCScOL9uAio4n0vbpSdNIsot8E59GhGqTIAzcvR2/gQXPZ1FHiPinOZj+rU1Hapx YsbNN9SrRkWmJfaKblaBkGbluEZP2ZAqaZSrYdIrNkNt+6xAQbcROLCv/dnKIX1J6FbZ dNLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1782879669; x=1783484469; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=wIXJacBAyEaKz61QqT13AHUcLwATDSXxJV4uZgWwmww=; b=DN2WJgYOUVqObjp27fb8eJ54k2AV6c0lelQF6XsS3aO0/kSsqJbGMhvd6v8VE85TkR 7xkqglwFUnWfgi0RuwCo02nvMNO0S7FlFaf9H3mis42e9gFLADQHI90hakgxXH2Tg/z6 AUyUZg5D0rNi4QNBo5S6qFCwq/t8d0eznjmcAY5+foOjWVV+BmZNI7TAXGvvRoEzpkOX GPUfTwGHedh/bYaq/7G86MpXKmNGsrjzVbi8FrdPdfBbByMfcrFLGYEvwkapQ8fI+PL3 ffHLoLZZtQhSNZaZC4WwAFWgo3jbuJc2T/uvcfv+rxZf45FtuTuu+TPpuAnDEcx3A4xc i1Ww== X-Forwarded-Encrypted: i=1; AHgh+RrTIHkKChedHnQgqvwscEqHWZ53kD/4yJ/wS4GB9/TYA3tBsHz2NwkX4J6EvbUNRV3zPSR4e6GuGd9rBdM=@vger.kernel.org X-Gm-Message-State: AOJu0YycA/HlVHlmFbK/b72HRM2RY1/ZqAgs23AsIk8mpJ5dCGtCujoH 5aA7u2ybWUgfqSZBTxk9dpXBy4IVuO/T4HJORbJgv1yuCyFrrc06yLtiRylsmjWKcnE= X-Gm-Gg: AfdE7cnKGxLx0P6DqlDhzQlX2KJrbsmFY8gTUFok7ki3kwlNfAJaKdE1hY3LprAPzO9 RxR2wGH65hNBJ7NWoG2zmXdoqbY4tKaJu7tZDQjFk2gqNtLuXJHy4VSe5mr9TWZNJpOjLDn7FFq 0dO/YL5MhCqGIFxR7IfSOnZAqjXUCp/Ulo+W1JwCPhhSZAp9V1wBDtmaoK3p5JWOLJj+66BBun9 RiBtI7G31TTtRiEbUSkyKmGAen/ADVeJnZLxfTrCXfK6Tvqe9whSF1UsfLRAuPXZZ9kusxeR9xx 67dEoIh8qj5pUnlHnQDvehAl+m/5O6UNr2Zz4mCt8lcO4+TWcA+LTOcxYbHRFIL6KUk06PWo01B qvxsGME3ZMtPkTe1b8rEQG01WOsF4kX3TaxBr+r1M33Hz0B8kUpLvvxWja7xzjeXtX7BjDt4OM0 SpfXfGSqur157mZg1e4+MjDZV0yREpwZApTB2sMFtKdWq6qQ== X-Received: by 2002:a17:902:d54f:b0:2ca:e3f:6a4a with SMTP id d9443c01a7336-2ca7e73b1bfmr1201915ad.21.1782879669155; Tue, 30 Jun 2026 21:21:09 -0700 (PDT) Received: from L6YN4KR4K9.bytedance.net ([139.177.225.232]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ca37c73a9csm24450865ad.21.2026.06.30.21.20.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 30 Jun 2026 21:21:08 -0700 (PDT) From: Yunhui Cui To: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, martin.lau@linux.dev, eddyz87@gmail.com, memxor@gmail.com, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, bjorn@kernel.org, pulehui@huawei.com, puranjay@kernel.org, thuth@redhat.com, ajones@ventanamicro.com, ben.dooks@codethink.co.uk, rkrcmar@ventanamicro.com, cuiyunhui@bytedance.com, samuel.holland@sifive.com, zong.li@sifive.com, conor.dooley@microchip.com, tglx@kernel.org, debug@rivosinc.com, seanwascoding@gmail.com, andybnac@gmail.com, menglong8.dong@gmail.com, cyrilbur@tenstorrent.com, wangruikang@iscas.ac.cn, atishp@rivosinc.com, apatel@ventanamicro.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, bpf@vger.kernel.org, arnd@arndb.de, nathan@kernel.org, nick.desaulniers+lkml@gmail.com, morbo@google.com, justinstitt@google.com, qingfang.deng@siflower.com.cn, linux-arch@vger.kernel.org, llvm@lists.linux.dev Subject: [PATCH v5 0/3] riscv: improve percpu helpers and PIO mapping Date: Wed, 1 Jul 2026 12:20:38 +0800 Message-Id: X-Mailer: git-send-email 2.39.2 (Apple Git-143) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Changes in v5: - Keep the PIO helper fix local to RISC-V: drop the generic HAS_IOPORT_MAP dependency change and the generic ioport_map() change from v4. - Add the missing linux/bits.h include for GENMASK and BITS_PER_BYTE. - Fix the 8/16-bit LR/SC fallback to mask subword results before writing them back. - Use early-clobber constraints in the 8/16-bit add_return LR/SC fallback. - Fix this_cpu_and_4/8 to pass the intended operand to RISC-V amoand. - Initialize the secondary idle task pcpu_offset before starting the CPU. Yunhui Cui (3): riscv: io: avoid null-pointer arithmetic in PIO helpers riscv: introduce percpu.h into include/asm riscv: store percpu offset into thread_info arch/riscv/include/asm/asm.h | 6 +- arch/riscv/include/asm/io.h | 26 ++- arch/riscv/include/asm/percpu.h | 287 +++++++++++++++++++++++++++ arch/riscv/include/asm/switch_to.h | 8 + arch/riscv/include/asm/thread_info.h | 3 +- arch/riscv/kernel/asm-offsets.c | 1 + arch/riscv/kernel/smpboot.c | 8 + arch/riscv/net/bpf_jit_comp64.c | 9 +- 8 files changed, 326 insertions(+), 22 deletions(-) create mode 100644 arch/riscv/include/asm/percpu.h -- 2.39.5