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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493e5a58853sm68494175e9.1.2026.07.08.14.18.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 14:18:34 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, matthias.p@variscite.com, Stefano Radaelli , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kees Cook , Tony Luck , "Guilherme G. Piccoli" Subject: [PATCH v1 0/3] Add support for Variscite VAR-SOM-AM62 and Symphony board Date: Wed, 8 Jul 2026 23:18:24 +0200 Message-ID: X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The series includes: - Device tree bindings documentation - SOM device tree with common peripherals - Symphony carrier board device tree with board-specific features The implementation follows the standard SOM + carrier board pattern where the SOM dtsi contains only peripherals mounted on the module, while carrier-specific interfaces are enabled in the board dts. Stefano Radaelli (3): dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62 arm64: dts: ti: Add support for Variscite VAR-SOM-AM62 arm64: dts: ti: var-som-am62: Add support for Variscite Symphony Board .../devicetree/bindings/arm/ti/k3.yaml | 6 + arch/arm64/boot/dts/ti/Makefile | 1 + .../boot/dts/ti/k3-am625-var-som-symphony.dts | 545 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi | 491 ++++++++++++++++ 4 files changed, 1043 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som-symphony.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am625-var-som.dtsi base-commit: 5c73cd9f0819c1c44e373e3dabb68318b1de1a12 -- 2.47.3