Re: [PATCH v10 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver

["Ramuthevar, Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>]

Hi,

On 27/2/2020 1:23 PM, Vignesh Raghavendra wrote:
>
> On 26/02/20 7:02 am, Ramuthevar, Vadivel MuruganX wrote:
>> Hi,
>>
>> On 25/2/2020 7:00 PM, Vignesh Raghavendra wrote:
>>> On 25/02/20 1:08 pm, Ramuthevar, Vadivel MuruganX wrote:
>>>>>>>> +
>>>>>>>> +  cdns,fifo-depth:
>>>>>>>> +    $ref: /schemas/types.yaml#/definitions/uint32
>>>>>>>> +    description:
>>>>>>>> +      Size of the data FIFO in words.
>>>>>>> A 4GB fifo is valid? Add some constraints.
>>>>>> 128 is valid, will update.
>>>>> Nope, the width of this field is 8bits -> 256 bytes
>>>> correct me if I am wrong, the width of this field is 4bits -> 128 bytes
>>>> (based on QUAD mode) .
>>> This has nothing to do with quad-mode. Its about how much SRAM amount of
>>> SRAM is present to buffer INDAC mode data. For TI platforms this is 256
>>> bytes.
>>> See CQSPI_REG_SRAMPARTITION definition in your datasheet.
>> Agreed, Thanks!
>> Yes , I have gone through it , Intel and Altera SoC's SRAM(act as
>> FIFO)size is 128 bytes and TI has 256 .
>> BTW old legacy DT binding mentioned size is 128, as per your earlier
>> suggestion you have mention that
>> keep the contents from old dt bindings as it is, so shall I keep 128/256?
> Old bindings does not impose a restriction that this needs to be 128
> bytes always (Its just the example that shows this property to be set to
> 128)
>
> What Rob is asking for is to add range of values that is valid for this
> field and not single value. So, both 128 and 256 bytes should be allowed
> as valid values for this property.

Thank you Vignesh, will add both.

Regards
Vadivel
>