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Mon, 15 Sep 2025 00:18:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHv532VEINyJKzuRlK20kwmlZeepldz6c/cEpUCjiPLpOVLguw7I7OkWPk+IJShxhNAMoygCA== X-Received: by 2002:a05:6a21:32a7:b0:251:e4b4:7a37 with SMTP id adf61e73a8af0-2602a894843mr15205936637.19.1757920694038; Mon, 15 Sep 2025 00:18:14 -0700 (PDT) Received: from [10.218.42.132] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-77607b18400sm12317233b3a.59.2025.09.15.00.18.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 Sep 2025 00:18:13 -0700 (PDT) Message-ID: Date: Mon, 15 Sep 2025 12:48:06 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 5/5] PCI: qcom: Add support for ECAM feature To: Bjorn Helgaas , Manivannan Sadhasivam , Krishna Chaitanya Chundru Cc: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Jingoo Han , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com References: <20250912210756.GA1639208@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20250912210756.GA1639208@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=M+5NKzws c=1 sm=1 tr=0 ts=68c7bdb7 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=IE8jCCfkdm6DJ3MH_s0A:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-GUID: fUQZNHY8plulCFymhxSSXdBL2PAJa9h_ X-Proofpoint-ORIG-GUID: fUQZNHY8plulCFymhxSSXdBL2PAJa9h_ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTE1MDA1NiBTYWx0ZWRfXzQxsssAxBa9j +D3RJwY3SfROP5KRn2jWRI2j+VOyTZkVd2TLEwwC7LyhR3UB+A9Awp3a4u1xDSO0v29pDx9WXv+ tyXABJtx1kUgYQPumM2ZTxnUmIwZn1UYhFLJNzat9CpJ6aOwJ1fm3D9DlAxaaKZtxLeNbpGPQ54 63i3E0EeSECBRq4THRYzFJkHOmlqYF4Z+mWXgtPWFZy7QDG91/yTrUBqQvjBngcdWeErrmukQQG VBbHwprd4d+Fzn3ZlVOmvcJHhlkrRCoxb+3eLs4suynIhqshq6cKPC2xJvA5Sd/9n0ytQJwKkoA b43tSZmbGfKMGOEQTH1MHO6bUE4t1KoFzBwtl4ZCt4vPrbAji9vCYhHHd/NWJCfP2Z51/b94tUz 5G8J7qMh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-15_03,2025-09-12_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 phishscore=0 adultscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509150056 On 9/13/2025 2:37 AM, Bjorn Helgaas wrote: > On Wed, Sep 03, 2025 at 02:57:21PM -0500, Bjorn Helgaas wrote: >> On Thu, Aug 28, 2025 at 01:04:26PM +0530, Krishna Chaitanya Chundru wrote: >>> The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register >>> gives us the offset from which ELBI starts. So override ELBI with the >>> offset from PARF_SLV_DBI_ELBI and cfg win to map these regions. >>> >>> On root bus, we have only the root port. Any access other than that >>> should not go out of the link and should return all F's. Since the iATU >>> is configured for the buses which starts after root bus, block the >>> transactions starting from function 1 of the root bus to the end of >>> the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going >>> outside the link through ECAM blocker through PARF registers. > >>> +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) >>> +{ >>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >>> + struct qcom_pcie *pcie = to_qcom_pcie(pci); >>> + u64 addr, addr_end; >>> + u32 val; >>> + >>> + /* Set the ECAM base */ >>> + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE); >>> + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_BASE_HI); >>> + >>> + /* >>> + * The only device on root bus is the Root Port. Any access to the PCIe >>> + * region will go outside the PCIe link. As part of enumeration the PCI >>> + * sw can try to read to vendor ID & device ID with different device >>> + * number and function number under root bus. As any access other than >>> + * root bus, device 0, function 0, should not go out of the link and >>> + * should return all F's. Since the iATU is configured for the buses >>> + * which starts after root bus, block the transactions starting from >>> + * function 1 of the root bus to the end of the root bus (i.e from >>> + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link. >>> + */ >>> + addr = pci->dbi_phys_addr + SZ_4K; >>> + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE); >>> + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BASE_HI); >>> + >>> + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE); >>> + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BASE_HI); >>> + >>> + addr_end = pci->dbi_phys_addr + SZ_1M - 1; >> >> I guess this is an implicit restriction to a single Root Port on the >> root bus at bb:00.0, right? So when the qcom IP eventually supports >> multiple Root Ports or even a single Root Port at a different >> device/function number, this would have to be updated somehow? > > The driver already supported ECAM in the existing "firmware_managed" > path (which looks untouched by this series and doesn't do any of this > iATU configuration). > The firmware_manages doesn't use dwc way of reading/writing to the config space, except for MSI's that doen't touch dwc core. > And IIUC, this series adds support for ECAM whenever the DT 'config' > range is sufficiently aligned. In this new ECAM support, it looks > like we look for and pay attention to 'bus-range' in this path: > > qcom_pcie_probe > dw_pcie_host_init > devm_pci_alloc_host_bridge > devm_of_pci_bridge_init > pci_parse_request_of_pci_ranges > devm_of_pci_get_host_bridge_resources > of_pci_parse_bus_range > of_property_read_u32_array(node, "bus-range", ...) > dw_pcie_host_get_resources > res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config") > pp->ecam_enabled = dw_pcie_ecam_enabled(pp, res) > > Since qcom_pci_config_ecam() doesn't look at the root bus number at > all, is this also an implicit restriction that the root bus must be > bus 0? Does qcom support root buses other than 0? > QCOM supports only bus 0. >>> + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT); >>> + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_WR_LIMIT_HI); >>> + >>> + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT); >>> + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_RD_LIMIT_HI); >>> + >>> + val = readl_relaxed(pcie->parf + PARF_SYS_CTRL); >>> + val |= PCIE_ECAM_BLOCKER_EN; >>> + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); >>> +} >>> + >>> static int qcom_pcie_start_link(struct dw_pcie *pci) >>> { >>> struct qcom_pcie *pcie = to_qcom_pcie(pci); >>> @@ -326,6 +383,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) >>> qcom_pcie_common_set_16gt_lane_margining(pci); >>> } >>> >>> + if (pci->pp.ecam_enabled) >>> + qcom_pci_config_ecam(&pci->pp); > > qcom_pcie_start_link() seems like a strange place to do this > ECAM-related iATU configuration. ECAM is a function of the host > bridge, not of any particular Root Port or link. > There is no API in pci-qcom.c related to the host bridge configuration currently, as we want to configure before enumeration starts we added it here, we can move this to qcom_pcie_host_init() if you are ok with it. - Krishna Chaitanya. >>> /* Enable Link Training state machine */ >>> if (pcie->cfg->ops->ltssm_enable) >>> pcie->cfg->ops->ltssm_enable(pcie);