Re: [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5

Abel Vesa
2025-10-09T09:53:29Z

On 25-09-25 12:02:28, Pankaj Patil wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> Add perst, wake and clkreq sideband signals and required regulators in
> PCIe5 controller and PHY device tree node.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 68 +++++++++++++++++++++++++++++++++
> 1 file changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> index 3f94bdf8b3ccfdff182005d67b8b3f84f956a430..03aacdb1dd7e2354fe31e63183519e53fa022829 100644
> --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
> @@ -107,6 +107,20 @@ port@1 {
> };
> };
> };
> +
> + vreg_nvme: regulator-nvme {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VREG_NVME_3P3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-0 = <&nvme_reg_en>;
> + pinctrl-names = "default";
> + };
> };
>
> &tlmm {

so tlmm already exists in here, but ...

> @@ -461,3 +475,57 @@ vreg_l4h_e0_1p2: ldo4 {
> &pmk8850_rtc {
> no-alarm;
> };
> +
> +&pmh0101_gpios {
> + nvme_reg_en: nvme-reg-en-state {
> + pins = "gpio14";
> + function = "normal";
> + bias-disable;
> + };
> +};
> +
> +&tlmm {

you add it here again.

> + pcie5_default: pcie5-default-state {
> + clkreq-n-pins {
> + pins = "gpio153";
> + function = "pcie5_clk_req_n";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +