[PATCH 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur

Pankaj Patil
2025-09-25T06:34:07Z

From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>

Add multiple instance of PMH0110 DT node, one for each assigned
SID for this PMIC on the spmi_bus0 and spmi_bus1 on the Glymur
CRD.

Take care to avoid compilation issue with the existing nodes by
gaurding each PMH0110 nodes with `#ifdef` for its corresponding
SID macro. So that only the nodes which have the their SID macro
defined are the only ones picked for compilation.

Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmh0110.dtsi | 66 ++++++++++++++++++++++++++++++++++-
1 file changed, 65 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/pmh0110.dtsi b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
index b99c33cba8860f1852231db33a127646c08c1e23..4a5c66e5c9fbc35cedb67601f4568844dc41fbea 100644
--- a/arch/arm64/boot/dts/qcom/pmh0110.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmh0110.dtsi
@@ -7,6 +7,8 @@
#include <dt-bindings/spmi/spmi.h>

&spmi_bus0 {
+
+#ifdef PMH0110_D_E0_SID
pmh0110_d_e0: pmic@PMH0110_D_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_D_E0_SID SPMI_USID>;
@@ -31,13 +33,14 @@ pmh0110_d_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif

+#ifdef PMH0110_F_E0_SID
pmh0110_f_e0: pmic@PMH0110_F_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_F_E0_SID SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
- status = "disabled";

pmh0110_f_e0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
@@ -56,7 +59,9 @@ pmh0110_f_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif

+#ifdef PMH0110_G_E0_SID
pmh0110_g_e0: pmic@PMH0110_G_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_G_E0_SID SPMI_USID>;
@@ -81,7 +86,36 @@ pmh0110_g_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+
+#ifdef PMH0110_H_E0_SID
+ pmh0110_h_e0: pmic@PMH0110_H_E0_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_H_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_h_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_H_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_h_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_h_e0_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif

+#ifdef PMH0110_I_E0_SID
pmh0110_i_e0: pmic@PMH0110_I_E0_SID {
compatible = "qcom,pmh0110", "qcom,spmi-pmic";
reg = <PMH0110_I_E0_SID SPMI_USID>;
@@ -106,4 +140,34 @@ pmh0110_i_e0_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+};
+
+&spmi_bus1 {
+#ifdef PMH0110_F_E1_SID
+ pmh0110_f_e1: pmic@PMH0110_F_E1_SID {
+ compatible = "qcom,pmh0110", "qcom,spmi-pmic";
+ reg = <PMH0110_F_E1_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0110_f_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0110_F_E1_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0110_f_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmh0110-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0110_f_e1_gpios 0 0 14>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
};

--
2.34.1