Re: [PATCH 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox

Bjorn Andersson
2025-09-25T17:06:43Z

On Thu, Sep 25, 2025 at 05:23:07PM +0900, Krzysztof Kozlowski wrote:
> On Thu, 25 Sept 2025 at 15:33, Pankaj Patil
> <pankaj.patil@oss.qualcomm.com> wrote:
> >
> > From: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> >
> > Enable pdp0 mailbox node on Glymur SoCs.
> >
> > Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
> > Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> > ---
> > arch/arm64/boot/dts/qcom/glymur.dtsi | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > index 66a548400c720474cde8a8b82ee686be507a795f..ae013c64e096b7c90c0aa4cfc50f078a85518acb 100644
> > --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> > @@ -4065,6 +4065,14 @@ watchdog@17600000 {
> > interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
> > };
> >
> > + pdp0_mbox: mailbox@17610000 {
> > + compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox";
> > + reg = <0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>;
> > + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> > + #mbox-cells = <1>;
> > + qcom,rx-chans = <0x7>;
> > + };
>
> Again one node per patch. this is really pointless, please read
> submitting patches before posting.
>

In this series I certainly agree with you.

This is most definitely part of the next patch, which is core support
that should have been part of the introduction of the CPU nodes in the
initial patch.

Regards,
Bjorn

> New Soc is one logical change. One.