Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts

Marc Zyngier
2025-09-25T13:02:39Z

On Thu, 25 Sep 2025 07:32:11 +0100,
Pankaj Patil <pankaj.patil@oss.qualcomm.com> wrote:
>
> Introduce initial device tree support for Glymur - Qualcomm's
> next-generation compute SoC and it's associated Compute Reference
> Device (CRD) platform.
>
> The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers,
> geni UART, interrupt controller, TLMM, reserved memory,
> interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD,
> SRAM, PSCI and pmu nodes.
>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++
> 3 files changed, 1346 insertions(+)
>

[...]

> + intc: interrupt-controller@17000000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0x17000000 0x0 0x10000>,
> + <0x0 0x17080000 0x0 0x480000>;
> +
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + #interrupt-cells = <3>;
> + interrupt-controller;
> +
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x40000>;

Drop these two properties. I assume that your GIC implementation is
compliant with the architecture, and doesn't need hand-holding.

> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + gic_its: gic-its@17040000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0x17040000 0x0 0x40000>;
> +
> + msi-controller;
> + #msi-cells = <1>;
> + };
> + };

[...]

> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

You are missing at one interrupt here, as the CPUs have both secure
security state and FEAT_VHE (hint: the EL2 virtual timer also has an
interrupt, usually on PPI 12).

M.

--
Without deviation from the norm, progress is not possible.