Re: [PATCH 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines

Abel Vesa
2025-10-11T11:06:49Z

On 25-09-25 12:02:12, Pankaj Patil wrote:
> From: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
>
> Add device tree support for QUPv3 serial engine protocols on Glymur.
> Glymur has 24 QUP serial engines across 3 QUP wrappers, each with
> support of GPI DMA engines.
>
> Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 43 +
> arch/arm64/boot/dts/qcom/glymur.dtsi | 3041 +++++++++++++++++++++++++++++--
> 2 files changed, 2936 insertions(+), 148 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index f1c5a0cb483670e9f8044e250950693b4a015479..8674465b22707207523caa8ad635d95a3396497a 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -707,6 +707,32 @@ gcc: clock-controller@100000 {
> #power-domain-cells = <1>;
> };
>
> + gpi_dma2: dma-controller@800000 {
> + compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma";
> + reg = <0 0x00800000 0 0x60000>;
> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <16>;
> + dma-channel-mask = <0x3f>;
> + #dma-cells = <3>;
> + iommus = <&apps_smmu 0xd76 0x0>;
> + status = "ok";

s/ok/okay/

Everywhere actually.