Re: [PATCH 23/24] arm64: dts: qcom: glymur: Add USB support

Abel Vesa
2025-11-03T15:26:25Z

On 25-09-25 12:02:31, Pankaj Patil wrote:
> From: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>
> The Glymur USB system contains 3 USB type C ports, and 1 USB multiport
> controller. This encompasses 5 SS USB QMP PHYs (3 combo and 2 uni) and 5
> M31 eUSB2 PHYs. The controllers are SNPS DWC3 based, and will use the
> flattened DWC3 QCOM design.
>
> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur-crd.dts | 243 ++++++++++++++
> arch/arm64/boot/dts/qcom/glymur.dtsi | 569 ++++++++++++++++++++++++++++++++
> 2 files changed, 812 insertions(+)
>

[...]

> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
> index 8a563d55bdd4902222039946dd75eaf4d3a4895b..c48d3a70820e551822c5322761528159da127ca6 100644
> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi
> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
> @@ -2417,6 +2417,231 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
> };
> };
>

[...]

> +
> + usb_1_ss0_qmpphy: phy@fd5000 {
> + compatible = "qcom,glymur-qmp-usb3-dp-phy";
> + reg = <0 0x00fd5000 0 0x8000>;
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux",
> + "ref",
> + "com_aux",
> + "usb3_pipe";

This one doesn't have a clkref. Why?

I just went through debugging an issue related to this clkref missing
on hamoa (my xps13, to be exact).

It seems whenever I drop the clk_disable_unused, I get a phy init
failure on usb_1_ss1_qmpphy, but never on the usb_1_ss0_qmpphy.
Traced it to the TCSR_USB4_1_CLKREF_EN which has no consumer.

Then came back to this patch and found that ss1 and ss2 have this
clkref and it is exactly as I found out on hamoa. So I guess we need
to fix hamoa.

Still, my question above remains...