[PATCH 13/24] arm64: dts: qcom: Update pmh0104 dtsi for Glymur CRD

Pankaj Patil
2025-09-25T06:34:03Z

From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>

Update the pmh0104.dtsi to include multiple instances of PMH0104
DT nodes, one for each SID assigned to this PMIC on the spmi_bus0
and spmi_bus1 in Glymur CRD board.

Take care to avoid compilation issue with the existing nodes by
gaurding each PMH0104 nodes with `#ifdef` for its corresponding
SID macro. So that only the nodes which have the their SID macro
defined are the only ones picked for compilation.

Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/pmh0104.dtsi | 84 +++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/pmh0104.dtsi b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
index f5393fdebe957ea0caf4bbc16117374b4759bda3..d3ea7486d842ec813a79268fc1466e1513426d78 100644
--- a/arch/arm64/boot/dts/qcom/pmh0104.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmh0104.dtsi
@@ -6,7 +6,63 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

+&spmi_bus0 {
+#ifdef PMH0104_I_E0_SID
+ pmh0104_i_e0: pmic@PMH0104_I_E0_SID {
+ compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+ reg = <PMH0104_I_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0104_i_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0104_I_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0104_i_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0104_i_e0_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
+
+#ifdef PMH0104_J_E0_SID
+ pmh0104_j_e0: pmic@PMH0104_J_E0_SID {
+ compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+ reg = <PMH0104_J_E0_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmh0104_j_e0_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0104_J_E0_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0104_j_e0_gpios: gpio@8800 {
+ compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0104_j_e0_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
+};
+
&spmi_bus1 {
+#ifdef PMH0104_J_E1_SID
pmh0104_j_e1: pmic@PMH0104_J_E1_SID {
compatible = "qcom,pmh0104", "qcom,spmi-pmic";
reg = <PMH0104_J_E1_SID SPMI_USID>;
@@ -30,4 +86,32 @@ pmh0104_j_e1_gpios: gpio@8800 {
#interrupt-cells = <2>;
};
};
+#endif
+
+#ifdef PMH0104_L_E1_SID
+ pmh0104_l_e1: pmic@PMH0104_L_E1_SID {
+ compatible = "qcom,pmh0104", "qcom,spmi-pmic";
+ reg = <PMH0104_L_E1_SID SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ pmh0104_l_e1_temp_alarm: temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00>;
+ interrupts = <PMH0104_L_E1_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ };
+
+ pmh0104_l_e1_gpios: gpio@8800 {
+ compatible = "qcom,pmh0104-gpio", "qcom,spmi-gpio";
+ reg = <0x8800>;
+ gpio-controller;
+ gpio-ranges = <&pmh0104_l_e1_gpios 0 0 8>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+#endif
};

--
2.34.1