From: Jes Sorensen <jes@linuxcare.com>
To: Manfred Spraul <manfred@colorfullife.com>
Cc: Mark Hemment <markhe@veritas.com>, linux-kernel@vger.kernel.org
Subject: Re: Q: explicit alignment control for the slab allocator
Date: 07 Mar 2001 21:02:03 +0100 [thread overview]
Message-ID: <d3lmqhny9w.fsf@lxplus015.cern.ch> (raw)
In-Reply-To: <Pine.LNX.4.21.0103011800460.11260-100000@alloc> <3A9EA940.CB82665C@colorfullife.com>
In-Reply-To: Manfred Spraul's message of "Thu, 01 Mar 2001 20:55:44 +0100"
>>>>> "Manfred" == Manfred Spraul <manfred@colorfullife.com> writes:
Manfred> Mark Hemment wrote:
>> As no one uses the feature it could well be broken, but is that a
>> reason to change its meaning?
Manfred> Some hardware drivers use HW_CACHEALIGN and assume certain
Manfred> byte alignments, and arm needs 1024 byte aligned blocks.
Isn't that just a reinvention of SMP_CACHE_BYTES? Or are there
actually machines out there where the inbetween CPU cache line size
differs from the between CPU and DMA controller cache line size?
Jes
next prev parent reply other threads:[~2001-03-07 20:03 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-03-01 17:26 Q: explicit alignment control for the slab allocator Manfred Spraul
2001-03-01 18:09 ` Mark Hemment
2001-03-01 19:55 ` Manfred Spraul
2001-03-01 20:28 ` Mark Hemment
2001-03-01 21:55 ` Manfred Spraul
2001-03-02 10:59 ` Mark Hemment
2001-03-02 11:51 ` Manfred Spraul
2001-03-02 12:39 ` Mark Hemment
2001-03-02 13:22 ` Manfred Spraul
2001-03-07 20:02 ` Jes Sorensen [this message]
2001-03-07 20:32 ` Manfred Spraul
2001-03-08 17:30 ` Jes Sorensen
2001-03-01 19:22 ` David S. Miller
2001-03-01 19:47 ` Manfred Spraul
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