From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C931F21A95D; Thu, 16 Apr 2026 06:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776320354; cv=none; b=DUUsz5wHR+rHoWi/rseqhvun1vNmvCqDh94dqRX4YmcDuNVAUr2mluKPHIr9DavNQRBoY0U2Ma3BCx18q1cAXoydxW9/GxkYEbO9zzpHx099BRrumXmaHv+NCqn5LRxMHX3y/znhbRJo0IWyPngL0eeUmNJnLabHJKuIMlftXYs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776320354; c=relaxed/simple; bh=qNrd3txvGZOPg0VoT9q3rBedmFvwr8GAJPvfgU9ToZg=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=mWc0lTISEZHOVoN8f5Ydnx1jOftZ9rUIRYnDkEYkLW3UzXjnl0/BdUd5tuvpSGMaVpSfyaCAk2UlvHlk7nkJd4zD9WDqTZbk5s5lBpLRrT+N8/+h0Y9QLeN6J2zhUO9vRu1ngBAmSltuidy9eTi4nhc5ywVloo6aGPbyc3FblOU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l0S0DHLW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l0S0DHLW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52436C2BCAF; Thu, 16 Apr 2026 06:19:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776320354; bh=qNrd3txvGZOPg0VoT9q3rBedmFvwr8GAJPvfgU9ToZg=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=l0S0DHLWlB+yr9O9wvzJccCI49pX553txPkOeqgZqP1vbpI/ajG0Kgc9ecpGHJrZ+ 8d3OKNGzL18SW2PSEko22GXeAGx35fOYNJyrAj2ZU5EDN0WXNekocJ00rkekNrNseG yDj/Aa/7GUq06JQL0/z+S1HczrHOhK4JXgDZ8WE79NNgNU1V/CH8Qj2jHiJ20JcC7n XoXQok6sVyr8NkhH+6eqOfzyqRNl6md2kSiLPFu3Pb5fdvCRZWGS+AWYczXAep8Sxk bOt98lNI9BXOpKqQzMlO9GphEHlAegzaNjeJayXtOjTYU47n92imZ3+aMIPz1MZ/gd yF5B80A1tJN2g== Message-ID: Date: Thu, 16 Apr 2026 08:19:09 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 5/5] arch: arm64: dts: qcom: Add support for PCIe3a To: Qiang Yu Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com> <20260412-glymur_gen5x8_phy_0413-v3-5-affcebc16b8b@oss.qualcomm.com> <20260415-pragmatic-termite-of-attraction-3dbab5@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 16/04/2026 05:24, Qiang Yu wrote: > On Wed, Apr 15, 2026 at 09:44:15AM +0200, Krzysztof Kozlowski wrote: >> On Sun, Apr 12, 2026 at 11:26:00PM -0700, Qiang Yu wrote: >>> Describe PCIe3a controller and PHY. Also add required system resources >>> like regulators, clocks, interrupts and registers configuration for PCIe3a. >>> >>> Signed-off-by: Qiang Yu >> >> subject: drop arch. >> >> Please use subject prefixes matching the subsystem. You can get them for >> example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory >> your patch is touching. For bindings, the preferred subjects are >> explained here: >> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters >> > > Thanks for pointing me the link. I’ll drop arch: in next version. > >>> --- >>> arch/arm64/boot/dts/qcom/glymur.dtsi | 316 ++++++++++++++++++++++++++++++++++- >>> 1 file changed, 315 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >>> index f23cf81ddb77a4138deeb4e00dd8b316930a2feb..c15f87c37ecbad72076a6c731f4959a1a8bd8425 100644 >>> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >>> @@ -736,7 +736,7 @@ gcc: clock-controller@100000 { >>> <0>, /* USB 2 Phy PCIE PIPEGMUX */ >>> <0>, /* USB 2 Phy PIPEGMUX */ >>> <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ >>> - <0>, /* PCIe 3a */ >>> + <&pcie3a_phy>, /* PCIe 3a */ >>> <&pcie3b_phy>, /* PCIe 3b */ >>> <&pcie4_phy>, /* PCIe 4 */ >>> <&pcie5_phy>, /* PCIe 5 */ >>> @@ -3640,6 +3640,320 @@ pcie3b_port0: pcie@0 { >>> }; >> >> ... >> >>>> + pcie3a_phy: phy@f00000 { >> >> Same comment as before. >> > > The existing PCIe/PHY nodes are not strictly ordered by address. Current > order is: Obviously we cannot even keep order of nodes when creating a new DTSI file from scratch. But adding @f00000 after @1c10000 makes even less sense, regardless how bad existing code is. Don't make it worse! This goes before phy@fa0000 > > - pcie4: pci@1bf0000 > - pcie4_phy: phy@1bf6000 > - pcie5: pci@1b40000 > - pcie5_phy: phy@1b50000 > - pcie6: pci@1c00000 > - pcie6_phy: phy@1c06000 > - pcie3b: pci@1b80000 > - pcie3a: pci@1c10000 (added in this patch) > - pcie3a_phy: phy@f00000 (added in this patch) > - pcie3b_phy: phy@f10000 > > Do you want me to reorder these nodes to follow strict address order? No, but don't add nodes randomly or following the previous broken order. Best regards, Krzysztof