From: Baolu Lu <baolu.lu@linux.intel.com>
To: Jacob Pan <jacob.jun.pan@linux.intel.com>,
LKML <linux-kernel@vger.kernel.org>,
iommu@lists.linux.dev, Jason Gunthorpe <jgg@nvidia.com>,
Joerg Roedel <joro@8bytes.org>,
Robin Murphy <robin.murphy@arm.com>,
Jean-Philippe Brucker <jean-philippe@linaro.com>,
dmaengine@vger.kernel.org, vkoul@kernel.org
Cc: baolu.lu@linux.intel.com, Will Deacon <will@kernel.org>,
David Woodhouse <dwmw2@infradead.org>,
Raj Ashok <ashok.raj@intel.com>,
"Tian, Kevin" <kevin.tian@intel.com>, Yi Liu <yi.l.liu@intel.com>,
"Yu, Fenghua" <fenghua.yu@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
Tony Luck <tony.luck@intel.com>,
"Zanussi, Tom" <tom.zanussi@intel.com>,
rex.zhang@intel.com, xiaochen.shen@intel.com,
narayan.ranganathan@intel.com
Subject: Re: [PATCH v9 0/7] Re-enable IDXD kernel workqueue under DMA API
Date: Tue, 11 Jul 2023 10:29:10 +0800 [thread overview]
Message-ID: <d6399f56-0528-d923-910c-822611137e2d@linux.intel.com> (raw)
In-Reply-To: <20230710101810.40098ce3@jacob-builder>
On 2023/7/11 1:18, Jacob Pan wrote:
> Hi Baolu, Joerg, and all,
Hi Jacob,
>
> Just wondering if there are more comments?
>
> Thanks,
>
> Jacob
>
> On Wed, 21 Jun 2023 13:59:40 -0700, Jacob Pan
> <jacob.jun.pan@linux.intel.com> wrote:
>
>> Hi Joerg and all,
>>
>> IDXD kernel work queues were disabled due to the flawed use of kernel VA
>> and SVA API.
>> Link:
>> https://lore.kernel.org/linux-iommu/20210511194726.GP1002214@nvidia.com/
>>
>> The solution is to enable it under DMA API where IDXD shared workqueue
>> users can use ENQCMDS to submit work on buffers mapped by DMA API.
>>
>> This patchset adds support for attaching PASID to the device's default
>> domain and the ability to allocate global PASIDs from IOMMU APIs. IDXD
>> driver can then re-enable the kernel work queues and use them under DMA
>> API.
>>
>> This depends on the IOASID removal series. (merged)
>> https://lore.kernel.org/all/ZCaUBJvUMsJyD7EW@8bytes.org/
>>
>>
>> Thanks,
>>
>> Jacob
>>
>> ---
>> Changelog:
>> v9:
>> - Fix an IDXD driver issue where user interrupt enable bit got
>> cleared during device enable/disable cycle. Reported and tested by
>> Tony Zhu<tony.zhu@intel.com>
>> - Rebased to v6.4-rc7
Thanks for fixing this.
It seems that you missed some review comments for v8. I can help to test
and merge when all comments are addressed.
Best regards,
baolu
next prev parent reply other threads:[~2023-07-11 2:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 20:59 [PATCH v9 0/7] Re-enable IDXD kernel workqueue under DMA API Jacob Pan
2023-06-21 20:59 ` [PATCH v9 1/7] iommu: Generalize PASID 0 for normal DMA w/o PASID Jacob Pan
2023-06-21 20:59 ` [PATCH v9 2/7] iommu: Move global PASID allocation from SVA to core Jacob Pan
2023-06-21 20:59 ` [PATCH v9 3/7] iommu/vt-d: Add domain_flush_pasid_iotlb() Jacob Pan
2023-06-21 20:59 ` [PATCH v9 4/7] iommu/vt-d: Remove pasid_mutex Jacob Pan
2023-06-21 20:59 ` [PATCH v9 5/7] iommu/vt-d: Make prq draining code generic Jacob Pan
2023-06-21 20:59 ` [PATCH v9 6/7] iommu/vt-d: Add set_dev_pasid callback for dma domain Jacob Pan
2023-06-21 20:59 ` [PATCH v9 7/7] dmaengine/idxd: Re-enable kernel workqueue under DMA API Jacob Pan
2023-07-10 17:18 ` [PATCH v9 0/7] Re-enable IDXD " Jacob Pan
2023-07-11 2:29 ` Baolu Lu [this message]
2023-07-12 5:51 ` Jacob Pan
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