Re: [PATCH v7 1/2] arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset

[Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>]

On 4/12/2022 12:35 AM, Matthias Kaehlcke wrote:
Thanks for your time Matthias!!!
> On Mon, Apr 11, 2022 at 07:23:03PM +0530, Srinivasa Rao Mandadapu wrote:
>> Add pinmux nodes for primary and secondary I2S for SC7280 based platforms.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
>> Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 14 +++++++++++
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi     | 41 ++++++++++++++++++++++++++++++++
>>   2 files changed, 55 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> index ecbf2b8..4ba2274 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
>> @@ -462,6 +462,20 @@
>>   	drive-strength = <10>;
>>   };
>>   
>> +&mi2s1_data0 {
>> +	drive-strength = <6>;
>> +	bias-disable;
>> +};
>> +
>> +&mi2s1_sclk {
>> +	drive-strength = <6>;
>> +	bias-disable;
>> +};
>> +
>> +&mi2s1_ws {
>> +	drive-strength = <6>;
>> +};
>> +
> With the new names the nodes should be inserted between 'dp_hot_plug_det' and
> 'pm7325_gpios'.
Okay. will change accordingly.
>
>>   &tlmm {
>>   	bt_en: bt-en {
>>   		pins = "gpio85";
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index f0b64be..8099c80 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -3527,6 +3527,31 @@
>>   				function = "pcie1_clkreqn";
>>   			};
>>   
>> +			mi2s0_data0: mi2s0-data0 {
> Similar as above, the new nodes should be inserted between
> 'edp_hot_plug_det' and 'pcie1_clkreq_n'.
Okay.
>
>> +				pins = "gpio98";
>> +				function = "mi2s0_data0";
>> +			};
>> +
>> +			mi2s0_data1: mi2s0-data1 {
>> +				pins = "gpio99";
>> +				function = "mi2s0_data1";
>> +			};
>> +
>> +			mi2s0_mclk: mi2s0-mclk {
>> +				pins = "gpio96";
>> +				function = "pri_mi2s";
>> +			};
>> +
>> +			mi2s0_sclk: mi2s0-sclk {
>> +				pins = "gpio97";
>> +				function = "mi2s0_sck";
>> +			};
>> +
>> +			mi2s0_ws: mi2s0-ws {
>> +				pins = "gpio100";
>> +				function = "mi2s0_ws";
>> +			};
>> +
>>   			qspi_clk: qspi-clk {
>>   				pins = "gpio14";
>>   				function = "qspi_clk";
>> @@ -4261,6 +4286,22 @@
>>   				drive-strength = <2>;
>>   				bias-bus-hold;
>>   			};
>> +
>> +			mi2s1_data0: mi2s1-data0 {
> see above
Okay.
>
>> +				pins = "gpio107";
>> +				function = "mi2s1_data0";
>> +			};
>> +
>> +			mi2s1_sclk: mi2s1-sclk {
>> +				pins = "gpio106";
>> +				function = "mi2s1_sck";
>> +			};
>> +
>> +			mi2s1_ws: mi2s1-ws {
>> +				pins = "gpio108";
>> +				function = "mi2s1_ws";
>> +			};