[PATCH v2 0/2] sched/fair: SMT-aware asymmetric CPU capacity

Andrea Righi
2026-04-03T05:39:16Z

This series attempts to improve SD_ASYM_CPUCAPACITY scheduling by introducing
SMT awareness.

= Problem =

Nominal per-logical-CPU capacity can overstate usable compute when an SMT
sibling is busy, because the physical core doesn't deliver its full nominal
capacity. So, several asym-cpu-capacity paths may pick high capacity idle CPUs
that are not actually good destinations.

= Solution =

This patch set aligns those paths with a simple rule already used elsewhere:
when SMT is active, prefer fully idle cores and avoid treating partially idle
SMT siblings as full-capacity targets where that would mislead load balance.

Patch set summary:
- Prefer fully-idle SMT cores in asym-capacity idle selection: in the wakeup
fast path, extend select_idle_capacity() / asym_fits_cpu() so idle
selection can prefer CPUs on fully idle cores.
- Reject misfit pulls onto busy SMT siblings on SD_ASYM_CPUCAPACITY.

This patch set has been tested on the new Vera Rubin platform, where SMT is
enabled and the firmware exposes small frequency variations (+/-~5%) as
differences in CPU capacity, resulting in SD_ASYM_CPUCAPACITY being set.

Without these patches, performance can drop by up to ~2x with CPU-intensive
workloads, because the SD_ASYM_CPUCAPACITY idle selection policy does not
account for busy SMT siblings.

Alternative approaches have been evaluated, such as equalizing CPU capacities,
either by exposing uniform values via firmware or normalizing them in the kernel
by grouping CPUs within a small capacity window (+-5%).

However, the SMT-aware SD_ASYM_CPUCAPACITY approach has shown better results so
far. Improving this policy also seems worthwhile in general, as future platforms
may enable SMT with asymmetric CPU topologies.

Performance results on Vera Rubin with SD_ASYM_CPUCAPACITY (mainline) vs
SD_ASYM_CPUCAPACITY + SMT:

- NVBLAS benchblas (one task / SMT core):

+---------------------------------+--------+
| Configuration | gflops |
+---------------------------------+--------+
| ASYM (mainline) + SIS_UTIL | 5478 |
| ASYM (mainline) + NO_SIS_UTIL | 5491 |
| | |
| NO ASYM + SIS_UTIL | 8912 |
| NO ASYM + NO_SIS_UTIL | 8978 |
| | |
| ASYM + SMT + SIS_UTIL | 9259 |
| ASYM + SMT + NO_SIS_UTIL | 9291 |
+---------------------------------+--------+

- DCPerf MediaWiki (all CPUs):

+---------------------------------+--------+--------+--------+--------+
| Configuration | rps | p50 | p95 | p99 |
+---------------------------------+--------+--------+--------+--------+
| ASYM (mainline) + SIS_UTIL | 7994 | 0.052 | 0.223 | 0.246 |
| ASYM (mainline) + NO_SIS_UTIL | 7993 | 0.052 | 0.221 | 0.245 |
| | | | | |
| NO ASYM + SIS_UTIL | 8113 | 0.067 | 0.184 | 0.225 |
| NO ASYM + NO_SIS_UTIL | 8093 | 0.068 | 0.184 | 0.223 |
| | | | | |
| ASYM + SMT + SIS_UTIL | 8129 | 0.076 | 0.149 | 0.188 |
| ASYM + SMT + NO_SIS_UTIL | 8138 | 0.076 | 0.148 | 0.186 |
+---------------------------------+--------+--------+--------+--------+

In the MediaWiki case SMT awareness is less impactful (compared to equalizing
CPU capacities), because for the majority of the run all CPUs are used, but it
still seems to provide some benefits at reducing tail latency.

See also:
- https://lore.kernel.org/lkml/20260324005509.1134981-1-arighi@nvidia.com
- https://lore.kernel.org/lkml/20260318092214.130908-1-arighi@nvidia.com

Changes in v2:
- Rework SMT awareness logic in select_idle_capacity() (K Prateek Nayak)
- Drop EAS and find_new_ilb() changes for now
- Link to v1: https://lore.kernel.org/all/20260326151211.1862600-1-arighi@nvidia.com

Andrea Righi (2):
sched/fair: Prefer fully-idle SMT cores in asym-capacity idle selection
sched/fair: Reject misfit pulls onto busy SMT siblings on asym-capacity

kernel/sched/fair.c | 44 +++++++++++++++++++++++++++++++++++++++-----
1 file changed, 39 insertions(+), 5 deletions(-)