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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDE4MCBTYWx0ZWRfX3V9jZ9RH2VEB rwXIcGKUNH0/4omaXMkoufQOq+7LoDb342Vw7T4HWWEJ8lZkwMCminL3+C3JlCnqxPN2+qUBwaz igGPiLpPDD8KNXxDvzYbuRjAUoMvY6bXNSX8i/MsAaA02ANQWSzL3/ldr+Z9VpO3ibIy2YgGli4 kVfm7mWO3UQhq32J3fxIlGlOgVFdz6PZKa7tEcoyOtF8KXjlp4I1Pl/t1iv5HTXUjFPVy3KEwYJ qJkR7xk8LOcZ1V5llJptbpB1tbG/MMIDtKeFR500YaEv9UrLobuAbUqQOaNQcY0gat11rgBjgf5 2h12vro+tcpHrcAp6ke7mWbD7iz/PhE7Sv+NOoBgGcDQDB3LlojcBq7TQ8J7G+LTNOQ/zG09QaX TjwIxGCW95vgM+1fitlom+8wF3WDO69v6vRzdVZ3tmQyx+IP+k5h6t5/rt2G89kzWwrsbA01 X-Proofpoint-ORIG-GUID: dmH2E5hQHIyuDDY2QBXm6PhuVLilgCl2 X-Proofpoint-GUID: dmH2E5hQHIyuDDY2QBXm6PhuVLilgCl2 X-Authority-Analysis: v=2.4 cv=IrMecK/g c=1 sm=1 tr=0 ts=68814edf cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=pSIa2sKh8ADkebnh61Ypzg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=sI7m75I2uMoaLRCfwtgA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_03,2025-07-23_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 malwarescore=0 adultscore=0 clxscore=1015 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230180 On 7/22/2025 8:22 PM, Konrad Dybcio wrote: > On 7/22/25 3:39 PM, Dmitry Baryshkov wrote: >> On Sun, Jul 20, 2025 at 05:46:08PM +0530, Akhil P Oommen wrote: >>> There are some special registers which are accessible even when GX power >>> domain is collapsed during an IFPC sleep. Accessing these registers >>> wakes up GPU from power collapse and allow programming these registers >>> without additional handshake with GMU. This patch adds support for this >>> special register write sequence. >>> >>> Signed-off-by: Akhil P Oommen >>> --- >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 63 ++++++++++++++++++++++++++++++- >>> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + >>> drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 20 +++++----- >>> 3 files changed, 73 insertions(+), 11 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> index 491fde0083a202bec7c6b3bca88d0e5a717a6560..8c004fc3abd2896d467a9728b34e99e4ed944dc4 100644 >>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c >>> @@ -16,6 +16,67 @@ >>> >>> #define GPU_PAS_ID 13 >>> >>> +static bool fence_status_check(struct msm_gpu *gpu, u32 offset, u32 value, u32 status, u32 mask) >>> +{ >>> + /* Success if !writedropped0/1 */ >>> + if (!(status & mask)) >>> + return true; >>> + >>> + udelay(10); >> >> Why do we need udelay() here? Why can't we use interval setting inside >> gmu_poll_timeout()? > > Similarly here: > > [...] > >>> + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, >>> + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) >>> + return 0; >>> + >>> + dev_err_ratelimited(gmu->dev, "delay in fenced register write (0x%x)\n", >>> + offset); >>> + >>> + /* Try again for another 1ms before failing */ >>> + gpu_write(gpu, offset, value); >>> + if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, >>> + fence_status_check(gpu, offset, value, status, mask), 0, 1000)) >>> + return 0; >>> + >>> + dev_err_ratelimited(gmu->dev, "fenced register write (0x%x) fail\n", >>> + offset); > > We may want to combine the two, so as not to worry the user too much.. > > If it's going to fail, I would assume it's going to fail both checks > (unless e.g. the bus is so congested a single write can't go through > to a sleepy GPU across 2 miliseconds, but that's another issue) In case of success, we cannot be sure if the first write went through. So we should poll separately. -Akhil. > > Konrad