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Subject: Re: [RFC 4/7] arm64: pmu: Add function implementation to update event
 index in userpage.
To:     Raphael Gault <raphael.gault@arm.com>,
        Peter Zijlstra <peterz@infradead.org>
Cc:     mark.rutland@arm.com, catalin.marinas@arm.com, will.deacon@arm.com,
        linux-kernel@vger.kernel.org, acme@kernel.org, mingo@redhat.com,
        linux-arm-kernel@lists.infradead.org
References: <20190528150320.25953-1-raphael.gault@arm.com>
 <20190528150320.25953-5-raphael.gault@arm.com>
 <20190529094659.GK2623@hirez.programming.kicks-ass.net>
 <42a937dd-5cf6-6738-6f69-005fce64138f@arm.com>
From:   Robin Murphy <robin.murphy@arm.com>
Message-ID: <d6f40c6c-6a73-bd7f-e384-050bd9428631@arm.com>
Date:   Wed, 29 May 2019 11:50:46 +0100
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On 29/05/2019 11:46, Raphael Gault wrote:
> Hi Peter,
> 
> On 5/29/19 10:46 AM, Peter Zijlstra wrote:
>> On Tue, May 28, 2019 at 04:03:17PM +0100, Raphael Gault wrote:
>>> +static int armv8pmu_access_event_idx(struct perf_event *event)
>>> +{
>>> +    if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
>>> +        return 0;
>>> +
>>> +    /*
>>> +     * We remap the cycle counter index to 32 to
>>> +     * match the offset applied to the rest of
>>> +     * the counter indeces.
>>> +     */
>>> +    if (event->hw.idx == ARMV8_IDX_CYCLE_COUNTER)
>>> +        return 32;
>>> +
>>> +    return event->hw.idx;
>>
>> Is there a guarantee event->hw.idx is never 0? Or should you, just like
>> x86, use +1 here?
>>
> 
> You are right, I should use +1 here. Thanks for pointing that out.

Isn't that already the case though, since we reserve index 0 for the 
cycle counter? I'm looking at ARMV8_IDX_TO_COUNTER() here...

Robin.