Re: [PATCH v4 RESEND 2/5] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers

[Like Xu <like.xu@linux.intel.com>]

On 2021/3/24 5:38, Peter Zijlstra wrote:
> On Mon, Mar 22, 2021 at 02:06:32PM +0800, Like Xu wrote:
>> If the platform supports LBR_INFO register, the x86_pmu.lbr_info will
>> be assigned in intel_pmu_?_lbr_init_?() and it's safe to expose LBR_INFO
> 
> You mean: intel_pmu_lbr_*init*(). '?' is a single character glob and
> you've got too many '_'s.
> 
>> in the x86_perf_get_lbr() directly, instead of relying on lbr_format check.
> 
> But, afaict, not every model calls one of those. CORE_YONAH for example
> doesn't.
> 
>> Also Architectural LBR has IA32_LBR_x_INFO instead of LBR_FORMAT_INFO_x
>> to hold metadata for the operation, including mispredict, TSX, and
>> elapsed cycle time information.
> 
> Relevance?
> 
> Wouldn't it be much simpler to simple say something like:
> 
>    "x86_pmu.lbr_info is 0 unless explicitly initialized, so there's no
>    point checking lbr_fmt"

Yes, it is simpler and I will apply it in the next version.

> 
>> Signed-off-by: Like Xu <like.xu@linux.intel.com>
>> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
>> Reviewed-by: Andi Kleen <ak@linux.intel.com>
>> ---
>>   arch/x86/events/intel/lbr.c | 4 +---
>>   1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
>> index 21890dacfcfe..355ea70f1879 100644
>> --- a/arch/x86/events/intel/lbr.c
>> +++ b/arch/x86/events/intel/lbr.c
>> @@ -1832,12 +1832,10 @@ void __init intel_pmu_arch_lbr_init(void)
>>    */
>>   int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
>>   {
>> -	int lbr_fmt = x86_pmu.intel_cap.lbr_format;
>> -
>>   	lbr->nr = x86_pmu.lbr_nr;
>>   	lbr->from = x86_pmu.lbr_from;
>>   	lbr->to = x86_pmu.lbr_to;
>> -	lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0;
>> +	lbr->info = x86_pmu.lbr_info;
>>   
>>   	return 0;
>>   }
>> -- 
>> 2.29.2
>>