Re: [PATCH v2 2/8] dt-bindings: clock: document 8ULP's SIM LPAV

Frank Li
2025-10-22T16:16:42Z

On Wed, Oct 22, 2025 at 10:08:41PM +0800, Peng Fan wrote:
> Hi Laurentiu,
>
> On Fri, Oct 17, 2025 at 04:20:19AM -0700, Laurentiu Mihalcea wrote:
> >From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> >
> >Add documentation for i.MX8ULP's SIM LPAV module.
> >
> >Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
> >---
> >+description:
> >+ The i.MX8ULP LPAV subsystem contains a block control module known as
> >+ SIM LPAV, which offers functionalities such as clock gating or reset
> >+ line assertion/de-assertion.
> >+
> >+properties:
> >+ compatible:
> >+ const: fsl,imx8ulp-sim-lpav
>
> This block also contains QoS registers, General purpose registers, HIFI

Qos should go though interconnect interface.

'#interconnect-cells' = <n>;

Frank

> general purpose registers, and others.
>
> I am not sure whether need to add a syscon fallback here. dt maintainer may
> help comment.
>
> Regards,
> Peng