Re: [PATCH v2 2/8] dt-bindings: clock: document 8ULP's SIM LPAV

Laurentiu Mihalcea
2025-10-27T15:17:47Z

On 10/22/2025 7:08 AM, Peng Fan wrote:
> Hi Laurentiu,
>
> On Fri, Oct 17, 2025 at 04:20:19AM -0700, Laurentiu Mihalcea wrote:
>> From: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>>
>> Add documentation for i.MX8ULP's SIM LPAV module.
>>
>> Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
>> ---
>> +description:
>> + The i.MX8ULP LPAV subsystem contains a block control module known as
>> + SIM LPAV, which offers functionalities such as clock gating or reset
>> + line assertion/de-assertion.
>> +
>> +properties:
>> + compatible:
>> + const: fsl,imx8ulp-sim-lpav
> This block also contains QoS registers, General purpose registers, HIFI
> general purpose registers, and others.
>
> I am not sure whether need to add a syscon fallback here. dt maintainer may
> help comment.

syscon programming model is NOT compatible with this programming model.

If you need access to other registers (not covered by reset/MUX/clock APIs), you're going to have to either go

through a subsystem API or manually create a device link between SIM LPAV and your consumer and then use

something like dev_get_regmap().

Either way, you need to make sure that you're using the same lock for register access.

as for the interconnect QoS-related stuff: can't really comment on this as I haven't worked

with it, nor do I have an use case for it ATM. However, the binding does need to be complete so

suggestions in this regard would be much appreciated.

>
> Regards,
> Peng