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Subject: Re: [PATCH 04/23] x86, tlb: make CR4-based TLB flushes more robust
To: Thomas Gleixner <tglx@linutronix.de>
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From: Dave Hansen <dave.hansen@linux.intel.com>
Message-ID: <d7db2bfd-e251-606f-a42f-55c9ef1aca55@linux.intel.com>
Date: Wed, 1 Nov 2017 15:24:03 -0700
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On 11/01/2017 02:25 PM, Thomas Gleixner wrote:
>>  	cr4 = this_cpu_read(cpu_tlbstate.cr4);
>> -	/* clear PGE */
>> -	native_write_cr4(cr4 & ~X86_CR4_PGE);
>> -	/* write old PGE again and flush TLBs */
>> +	/*
>> +	 * This function is only called on systems that support X86_CR4_PGE
>> +	 * and where always set X86_CR4_PGE.  Warn if we are called without
>> +	 * PGE set.
>> +	 */
>> +	WARN_ON_ONCE(!(cr4 & X86_CR4_PGE));
> Because if CR4_PGE is not set, this warning triggers. So this defeats the
> toggle mode you are implementing.

The warning is there because there is probably plenty of *other* stuff
that breaks if we have X86_FEATURE_PGE=1, but CR4.PGE=0.

The point of this was to make this function do the right thing no matter
what, but warn if it gets called in an unexpected way.