From: Stephen Boyd <sboyd@kernel.org>
To: Peng Fan (OSS) <peng.fan@oss.nxp.com>,
abelvesa@kernel.org, festevam@gmail.com, kernel@pengutronix.de,
mturquette@baylibre.com, s.hauer@pengutronix.de,
shawnguo@kernel.org
Cc: imx@lists.linux.dev, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH] clk: imx: lpcg-scu: SW workaround for errata (e10858)
Date: Wed, 28 Feb 2024 14:18:03 -0800 [thread overview]
Message-ID: <d81a0e5a477f03c248111f515ae2e3be.sboyd@kernel.org> (raw)
In-Reply-To: <20240228082649.1633083-1-peng.fan@oss.nxp.com>
Quoting Peng Fan (OSS) (2024-02-28 00:26:49)
> diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c
> index dd5abd09f3e2..b30d0f8b5bca 100644
> --- a/drivers/clk/imx/clk-lpcg-scu.c
> +++ b/drivers/clk/imx/clk-lpcg-scu.c
> @@ -6,6 +6,7 @@
>
> #include <linux/bits.h>
> #include <linux/clk-provider.h>
> +#include <linux/delay.h>
> #include <linux/err.h>
> #include <linux/io.h>
> #include <linux/slab.h>
> @@ -41,6 +42,31 @@ struct clk_lpcg_scu {
>
> #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)
>
> +/* e10858 -LPCG clock gating register synchronization errata */
> +static void do_lpcg_workaround(u32 rate, void __iomem *reg, u32 val)
unsigned long rate
> +{
> + writel(val, reg);
> +
> + if (rate >= 24000000 || rate == 0) {
> + u32 reg1;
Please declare this variable at the start of the function.
> +
> + /*
> + * The time taken to access the LPCG registers from the AP core
> + * through the interconnect is longer than the minimum delay
> + * of 4 clock cycles required by the errata.
> + * Adding a readl will provide sufficient delay to prevent
> + * back-to-back writes.
> + */
> + reg1 = readl(reg);
> + } else {
> + /*
> + * For clocks running below 24MHz, wait a minimum of
> + * 4 clock cycles.
> + */
> + ndelay(4 * (DIV_ROUND_UP(1000000000, rate)));
> + }
> +}
> +
> static int clk_lpcg_scu_enable(struct clk_hw *hw)
> {
> struct clk_lpcg_scu *clk = to_clk_lpcg_scu(hw);
> @@ -57,7 +83,8 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw)
> val |= CLK_GATE_SCU_LPCG_HW_SEL;
>
> reg |= val << clk->bit_idx;
> - writel(reg, clk->reg);
> +
> + do_lpcg_workaround(clk_hw_get_rate(hw), clk->reg, reg);
I'd prefer the name had 'writel' in it somewhere.
>
> spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
>
next prev parent reply other threads:[~2024-02-28 22:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-28 8:26 [PATCH] clk: imx: lpcg-scu: SW workaround for errata (e10858) Peng Fan (OSS)
2024-02-28 19:17 ` Frank Li
2024-02-28 22:18 ` Stephen Boyd [this message]
-- strict thread matches above, loose matches on Subject: below --
2020-09-08 9:14 peng.fan
2020-09-08 10:18 ` Abel Vesa
2020-09-08 12:10 ` Peng Fan
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