From: Stephen Boyd <sboyd@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>,
Yang Xiwen via B4 Relay
<devnull+forbidden405.outlook.com@kernel.org>,
forbidden405@outlook.com
Cc: David Yang <mmyangfl@gmail.com>,
Igor Opaniuk <igor.opaniuk@foundries.io>,
Jorge Ramirez-Ortiz Gmail <jorge.ramirez.ortiz@gmail.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Yang Xiwen <forbidden405@outlook.com>
Subject: Re: [PATCH RFC 1/2] clk: hisilicon: rename hi3519 PLL registration function
Date: Wed, 10 Apr 2024 23:52:24 -0700 [thread overview]
Message-ID: <d8dc639c2c6d188d2ce3728573d9a53d.sboyd@kernel.org> (raw)
In-Reply-To: <20240225-pll-v1-1-fad6511479c6@outlook.com>
Quoting Yang Xiwen via B4 Relay (2024-02-24 08:56:09)
> diff --git a/drivers/clk/hisilicon/clk-hi3559a.c b/drivers/clk/hisilicon/clk-hi3559a.c
> index ff4ca0edce06..77fa4203a428 100644
> --- a/drivers/clk/hisilicon/clk-hi3559a.c
> +++ b/drivers/clk/hisilicon/clk-hi3559a.c
> @@ -452,7 +452,7 @@ static const struct clk_ops hisi_clk_pll_ops = {
> .recalc_rate = clk_pll_recalc_rate,
> };
>
> -static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
> +static void _hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
Prefix it with hi3559a then to be SoC specific please. But this is also
static so I'm not sure why this patch is needed at all.
next prev parent reply other threads:[~2024-04-11 6:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-24 16:56 [PATCH RFC 0/2] clk: hisilicon: add support for PLL Yang Xiwen via B4 Relay
2024-02-24 16:56 ` [PATCH RFC 1/2] clk: hisilicon: rename hi3519 PLL registration function Yang Xiwen via B4 Relay
2024-04-11 6:52 ` Stephen Boyd [this message]
2024-04-11 7:44 ` Yang Xiwen
2024-04-11 7:53 ` Stephen Boyd
2024-04-11 10:31 ` Yang Xiwen
2024-04-12 3:03 ` Stephen Boyd
2024-02-24 16:56 ` [PATCH RFC 2/2] clk: hisilicon: add support for PLL Yang Xiwen via B4 Relay
2024-04-11 6:59 ` Stephen Boyd
2024-04-11 7:54 ` Yang Xiwen
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