From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0066EC04A6A for ; Fri, 4 Aug 2023 07:55:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234038AbjHDHzg (ORCPT ); Fri, 4 Aug 2023 03:55:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234011AbjHDHzc (ORCPT ); Fri, 4 Aug 2023 03:55:32 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C0884488; Fri, 4 Aug 2023 00:55:30 -0700 (PDT) Received: from [172.20.10.2] (unknown [109.166.131.29]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: ehristev) by madras.collabora.co.uk (Postfix) with ESMTPSA id D642E66071B9; Fri, 4 Aug 2023 08:55:26 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1691135728; bh=7r9GShoKmneDSmX53QgcnbJVa5KPZiLE0eJ/AjUQWvY=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Cbn7oSahDKki5y/OmUcpKp1jjzOPgQjLRBIMBYtWUBhNzAoQNrEbfAe/ryEDD2Jw+ UXMrqXfCnRqixCkB+NRgSHiLoWpeCaWW/7Czx/dTgFIYPFdbc/dCs+fOg33O4tqvWY P2fckGcjMJAEpb7Qpu2CVAY2/G9/c+zJspITRV+EvZrsYFhZzBFGjWERkCHyHXfRQ6 Ku4wHjtMJHvkWbyuTNNSLtGxUSbsvMSy3B8RcwjaRpRBx3wcYcuZYkXpzfK8E3+PzN h4u9HbgqI5TN+l2oxA6ymCSvR2Rq8kjCkJpAQxb42d4i88mJeJOPBJ2wTrSOggpBDZ YarRuShh65W8A== Message-ID: Date: Fri, 4 Aug 2023 10:55:23 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [v3] media: mediatek: vcodec: fix AV1 decoding on MT8188 To: Xiaoyong Lu , Yunfei Dong , Alexandre Courbot , Nicolas Dufresne , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin , Andrew-CT Chen , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Tomasz Figa Cc: George Sun , Hsin-Yi Wang , Fritz Koenig , Daniel Vetter , dri-devel , Irui Wang , Steve Cho , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com References: <20230803111017.2418-1-xiaoyong.lu@mediatek.com> Content-Language: en-US From: Eugen Hristev In-Reply-To: <20230803111017.2418-1-xiaoyong.lu@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Xiaoyong, On 8/3/23 14:10, Xiaoyong Lu wrote: > Fix AV1 decoding failure when the iova is 36bit. > > Before this fix, the decoder was accessing incorrect addresses with 36bit > iova tile buffer, leading to iommu faults. > > Fixes: 2f5d0aef37c6 ("media: mediatek: vcodec: support stateless AV1 decoder") > Signed-off-by: Xiaoyong Lu > --- > Changes from v2: > > - refine commit subject and message > > Changes from v1: > > - prefer '|' rather than '+' > - prefer '&' rather than shift operation > - add comments for address operations > > v1: > - VDEC HW can access tile buffer and decode normally. > - Test ok by mt8195 32bit and mt8188 36bit iova. > > --- > .../mediatek/vcodec/vdec/vdec_av1_req_lat_if.c | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > index 404a1a23fd402..e9f2393f6a883 100644 > --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_av1_req_lat_if.c > @@ -1658,9 +1658,9 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins > u32 allow_update_cdf = 0; > u32 sb_boundary_x_m1 = 0, sb_boundary_y_m1 = 0; > int tile_info_base; > - u32 tile_buf_pa; > + u64 tile_buf_pa; > u32 *tile_info_buf = instance->tile.va; > - u32 pa = (u32)bs->dma_addr; > + u64 pa = (u64)bs->dma_addr; If it this is a dma address, can't we use dma_addr_t ? isn't it more generic? Or maybe you have a specific reason not to ? > > if (uh->disable_cdf_update == 0) > allow_update_cdf = 1; > @@ -1673,8 +1673,12 @@ static void vdec_av1_slice_setup_tile_buffer(struct vdec_av1_slice_instance *ins > tile_info_buf[tile_info_base + 0] = (tile_group->tile_size[tile_num] << 3); > tile_buf_pa = pa + tile_group->tile_start_offset[tile_num]; > > - tile_info_buf[tile_info_base + 1] = (tile_buf_pa >> 4) << 4; > - tile_info_buf[tile_info_base + 2] = (tile_buf_pa % 16) << 3; > + /* save av1 tile high 4bits(bit 32-35) address in lower 4 bits position > + * and clear original for hw requirement. > + */ > + tile_info_buf[tile_info_base + 1] = (tile_buf_pa & 0xFFFFFFF0ull) | > + ((tile_buf_pa & 0xF00000000ull) >> 32); > + tile_info_buf[tile_info_base + 2] = (tile_buf_pa & 0xFull) << 3; Would it be better to use GENMASK if you plan to mask out some of the bits in the tile_buf_pa ? > > sb_boundary_x_m1 = > (tile->mi_col_starts[tile_col + 1] - tile->mi_col_starts[tile_col] - 1) & Greetings, Eugen