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Tue, 07 Jul 2026 09:34:34 -0700 (PDT) Received: from [10.254.183.223] ([149.199.62.131]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-69a19d78a08sm6832401a12.18.2026.07.07.09.34.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 07 Jul 2026 09:34:32 -0700 (PDT) Message-ID: Date: Tue, 7 Jul 2026 18:34:24 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/5] dt-bindings: clock: Move xlnx,zynqmp-clk to its own schema To: Rob Herring , Michal Simek Cc: linux-kernel@vger.kernel.org, git@amd.com, Conor Dooley , Krzysztof Kozlowski , Michael Turquette , Stephen Boyd , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , kishore Manne , "moderated list:ARM/ZYNQ ARCHITECTURE" , "open list:COMMON CLK FRAMEWORK" References: <23d848e29176706548612c4a0751481d46176f11.1780499520.git.michal.simek@amd.com> Content-Language: en-US From: Michal Simek In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 7/7/26 17:55, Rob Herring wrote: > On Wed, Jun 3, 2026 at 10:12 AM Michal Simek wrote: >> >> The ZynqMP clock controller binding shares only #clock-cells with the >> Versal bindings. Move it to a dedicated xlnx,zynqmp-clk.yaml schema. >> Also remove "(Optional clock)" from clock description because it is visible >> from schema itself. >> >> Suggested-by: Rob Herring >> Signed-off-by: Michal Simek >> --- >> >> Changes in v3: >> - Cover change in zynqmp-firmware.yaml >> - Move clock-cells to be the last in the example >> - Remove comment around (Optional clock) which is obvious from schema >> itself >> >> Changes in v2: >> - New patch in series >> - Split zynqmp-clk from versal-clk >> >> .../bindings/clock/xlnx,versal-clk.yaml | 50 +------------- >> .../bindings/clock/xlnx,zynqmp-clk.yaml | 68 +++++++++++++++++++ >> .../firmware/xilinx/xlnx,zynqmp-firmware.yaml | 7 +- >> 3 files changed, 76 insertions(+), 49 deletions(-) >> create mode 100644 Documentation/devicetree/bindings/clock/xlnx,zynqmp-clk.yaml > > This is now causing warnings in linux-next: > > /builds/robherring/linux-dt/Documentation/devicetree/bindings/clock/xlnx,versal-clk.example.dtb: > zynqmp-firmware (xlnx,zynqmp-firmware): > clock-controller:clock-names:0: 'pss_ref_clk' was expected > from schema $id: > http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml > /builds/robherring/linux-dt/Documentation/devicetree/bindings/clock/xlnx,versal-clk.example.dtb: > zynqmp-firmware (xlnx,zynqmp-firmware): > clock-controller:clock-names:1: 'video_clk' was expected > from schema $id: > http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml > /builds/robherring/linux-dt/Documentation/devicetree/bindings/clock/xlnx,versal-clk.example.dtb: > zynqmp-firmware (xlnx,zynqmp-firmware): clock-controller:clock-names: > ['ref', 'pl_alt_ref'] is too short > from schema $id: > http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml > /builds/robherring/linux-dt/Documentation/devicetree/bindings/clock/xlnx,versal-clk.example.dtb: > zynqmp-firmware (xlnx,zynqmp-firmware): clock-controller:clocks: > [[4294967295], [4294967295]] is too short > from schema $id: > http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml > /builds/robherring/linux-dt/Documentation/devicetree/bindings/clock/xlnx,versal-clk.example.dtb: > zynqmp-firmware (xlnx,zynqmp-firmware): clock-controller:compatible:0: > 'xlnx,zynqmp-clk' was expected > from schema $id: > http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml I will look at it. Thanks for reporting it. Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP/Versal ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal/Versal NET SoCs TF-A maintainer - Xilinx ZynqMP/Versal/Versal NET SoCs