Re: [PATCH 10/15] KVM: x86/pmu: Emulate the GLOBAL_STATUS_SET and GLOBAL_INUSE MSRs

["Chen, Zide" <zide.chen@intel.com>]

On 7/7/2026 1:34 PM, Zide Chen wrote:
> Intel PerfMon v4 introduces IA32_PERF_GLOBAL_STATUS_SET (0x391) to
> allow software to set individual bits in the global status MSR. Reads
> of IA32_PERF_GLOBAL_STATUS_SET always return zero.
> 
> IA32_PERF_GLOBAL_INUSE (0x392) is also introduced in v4, to track
> which counters and the PMI are currently claimed by other agents,
> allowing independent software agents to check counter availability
> without a shared scheduler arbitrating between them.
> 
> IA32_PERF_GLOBAL_INUSE is an R/O MSR, and any write attempt results
> in a #GP.
> 
> Neither MSR is part of the VM state, so they don't need to be
> advertised to userspace, nor saved and restored during live
> migration.
> 
> Originally-by: Yang Weijiang <weijiang.yang@intel.com>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
>  arch/x86/include/asm/msr-index.h |  4 ++++
>  arch/x86/kvm/pmu.c               |  9 ++++++++
>  arch/x86/kvm/vmx/pmu_intel.c     | 38 ++++++++++++++++++++++++++++++++
>  arch/x86/kvm/vmx/vmx.c           |  4 ++++
>  4 files changed, 55 insertions(+)
> 
> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> index feee92aab504..46ca6b56628b 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -1241,6 +1241,10 @@
>  #define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
>  #define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
>  #define MSR_CORE_PERF_GLOBAL_STATUS_SET	0x00000391
> +#define MSR_CORE_PERF_GLOBAL_INUSE	0x00000392
> +
> +/* Intel IA32_PERF_GLOBAL_INUSE MSR */
> +#define PERF_GLOBAL_INUSE_PMI_INUSE	BIT_ULL(63)
>  
>  #define MSR_PERF_METRICS		0x00000329
>  
> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
> index bc2ca60114e9..7d58f7a2a2db 100644
> --- a/arch/x86/kvm/pmu.c
> +++ b/arch/x86/kvm/pmu.c
> @@ -834,6 +834,8 @@ bool kvm_pmu_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
>  	case MSR_CORE_PERF_GLOBAL_CTRL:
>  	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
>  		return kvm_pmu_has_perf_global_ctrl(vcpu_to_pmu(vcpu));
> +	case MSR_CORE_PERF_GLOBAL_STATUS_SET:
> +		return vcpu_to_pmu(vcpu)->version > 3;
>  	default:
>  		break;
>  	}
> @@ -867,6 +869,7 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
>  	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
>  	case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
> +	case MSR_CORE_PERF_GLOBAL_STATUS_SET:
>  		msr_info->data = 0;
>  		break;
>  	default:
> @@ -933,6 +936,12 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  		if (!msr_info->host_initiated)
>  			pmu->global_status &= ~data;
>  		break;
> +	case MSR_CORE_PERF_GLOBAL_STATUS_SET:
> +		if (data & pmu->global_status_rsvd)
> +			return 1;
> +		if (!msr_info->host_initiated)
> +			pmu->global_status |= data;
> +		break;
>  	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET:
>  		if (!msr_info->host_initiated)
>  			pmu->global_status |= data & ~pmu->global_status_rsvd;
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index 425f17aa9be2..cb6f9c272e03 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -205,6 +205,8 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
>  	switch (msr) {
>  	case MSR_CORE_PERF_FIXED_CTR_CTRL:
>  		return kvm_pmu_has_perf_global_ctrl(pmu);
> +	case MSR_CORE_PERF_GLOBAL_INUSE:
> +		return pmu->version > 3;
>  	case MSR_PERF_METRICS:
>  		return kvm_vcpu_has_perf_metrics(vcpu);
>  	case MSR_IA32_PEBS_ENABLE:
> @@ -354,6 +356,40 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu,
>  	return true;
>  }
>  
> +static int intel_pmu_get_global_inuse(struct kvm_vcpu *vcpu,
> +				      struct msr_data *msr_info)

Since intel_pmu_get_global_inuse() cannot realistically fail, returning
an int solely to propagate 0 is unnecessary. Change it to return the
emulated GLOBAL_INUSE value directly and remove the now-unused msr_info
parameter.

> +{
> +	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
> +	unsigned long fixed_mask = kvm_fixed_pmc_mask(pmu);
> +	unsigned long gp_mask = kvm_gp_pmc_mask(pmu);
> +	bool pmi_inuse = false;
> +	u32 fixed_ctrl;
> +	u64 eventsel;
> +	int i;
> +
> +	msr_info->data = 0;
> +	kvm_for_each_set_pmc_idx(i, gp_mask, INTEL_GP) {
> +		eventsel = pmu->gp_counters[i].eventsel;
> +
> +		if (eventsel & ARCH_PERFMON_EVENTSEL_EVENT)
> +			msr_info->data |= BIT_ULL(i);
> +		pmi_inuse |= eventsel & ARCH_PERFMON_EVENTSEL_INT;
> +	}
> +	kvm_for_each_set_pmc_idx(i, fixed_mask, INTEL_FIXED) {
> +		fixed_ctrl = fixed_ctrl_field(pmu->fixed_ctr_ctrl, i);
> +
> +		if (fixed_ctrl & (INTEL_FIXED_0_KERNEL | INTEL_FIXED_0_USER))
> +			msr_info->data |= BIT_ULL(KVM_FIXED_PMC_BASE_IDX + i);
> +		pmi_inuse |= fixed_ctrl & INTEL_FIXED_0_ENABLE_PMI;
> +	}
> +	pmi_inuse |= pmu->pebs_enable;
> +
> +	if (pmi_inuse)
> +		msr_info->data |= PERF_GLOBAL_INUSE_PMI_INUSE;
> +
> +	return 0;
> +}
> +
>  static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  {
>  	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
> @@ -364,6 +400,8 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  	case MSR_CORE_PERF_FIXED_CTR_CTRL:
>  		msr_info->data = pmu->fixed_ctr_ctrl;
>  		break;
> +	case MSR_CORE_PERF_GLOBAL_INUSE:
> +		return intel_pmu_get_global_inuse(vcpu, msr_info);

Additional benefit is to keep code style consistency:

               msr_info->data = intel_pmu_get_global_inuse(vcpu);
               break;

>  	case MSR_PERF_METRICS:
>  		msr_info->data = pmu->perf_metrics;
>  		break;