[PATCH 0/2] Fix V1P8_SIGNAL_ENA and HIGH_SPEED_ENA

Judith Mendez
2025-04-07T22:27:09Z

For all TI devices, timing was closed For Legacy and HS modes in
half cycle timing, where data is launched on the negative edge of
clock and latched on the following positive edge of clock. The
switch to full cycle timing happens when any of HIGH_SPEED_ENA,
V1P8_SIGNAL_ENA, or UHS_MODE_SELECT is set.

Currently HIGH_SPEED_ENA is set for HS modes and violates timing
requirements for TI devices so add a .set_hs_ena callback in
sdhci_am654 driver so that HIGH_SPEED_ENA is not set for this mode.

There are eMMC boot failures seen with V1P8_SIGNAL_ENA with a
specific Kingston eMMC due to the sequencing when enumerating to
HS200 mode. Since V1P8_SIGNAL_ENA is optional for eMMC, do not
set V1P8_SIGNAL_ENA be default. This fix was previously merged in
the kernel, but was reverted due to the "heuristics for enabling
the quirk"[0]. The new implementation applies the quirk based-off of
bus width, which should not be an issue since there is no internal
LDO for MMC0 8bit wide interface and hence V1P8_SIGNAL_ENA should only
effect timing for MMC0 interface.

[0] https://lore.kernel.org/linux-mmc/20250127-am654-mmc-regression-v2-1-9bb39fb12810@solid-run.com/

Judith Mendez (2):
PENDING: mmc: sdhci*: Add set_hs_ena to sdhci_ops
mmc: sdhci_am654: Add sdhci_am654_start_signal_voltage_switch

drivers/mmc/host/sdhci.c | 55 +++++++++++++++++++++-------------
drivers/mmc/host/sdhci.h | 2 ++
drivers/mmc/host/sdhci_am654.c | 48 +++++++++++++++++++++++++++++
3 files changed, 85 insertions(+), 20 deletions(-)

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2.49.0