Re: I/O page faults from 8250_mid PCIe UART after TIOCVHANGUP

["Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>]

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On Mon, 19 Sep 2022, Andy Shevchenko wrote:

> On Thu, Sep 15, 2022 at 07:27:45PM +0300, Ilpo Järvinen wrote:
> > On Wed, 14 Sep 2022, Andy Shevchenko wrote:
> > > On Wed, Sep 14, 2022 at 02:10:44PM +0300, Lennert Buytenhek wrote:
> > > > On Wed, Sep 14, 2022 at 01:09:40PM +0300, Andy Shevchenko wrote:
> 
> ...
> 
> > -	/*
> > -	 * The above check will only give an accurate result the first time
> > -	 * the port is opened so this value needs to be preserved.
> > -	 */
> 
> Side note: I haven't got why you removed this comment (it may be some staled
> info, but shouldn't be done in the separate change then?).

I cleaned up this part in v2 (as you probably noticed). I was just an 
artifact of how the fix got initially made.

I've also located the place where the comment belongs to. "The above 
check" refers to the THRE test. However, I don't fully understand the 
comment itself, that is, why the test is claimed to only work for for the 
first time. As long as FIFO is cleared beforehand, I think it should work 
on other times too.


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 i.