From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCCD123BD05 for ; Thu, 2 Apr 2026 22:12:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775167923; cv=none; b=T/C9U4TPZr7o0Crl+jaBwhQl8grJOTxxloivcowLLVyEKFeh7idXgVm2LVQZI6TJaA+JDnjyOWhpsDl1gjCZtPv0t8+KxNdHEEcBGm4ji1Ht7bZhmvNioTaNsTuIIhQKn+UQPJOc4GXNdbAx1mOEv9h5ENss3KNohwFj5U9PxBQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775167923; c=relaxed/simple; bh=yPWQ8Lu8w3RP+W5pBE5AC0381sEeBDUcYqrijLfEx9Y=; h=Date:From:To:cc:Subject:In-Reply-To:Message-ID:References: MIME-Version:Content-Type; b=pAp0567rddtIMZ6z1kdrW7guNrXHvVEzyTJeRSPTB42BujAwSUGd0h7OpXjlLPTZmleQfogSEl/chNs/uMqkr0bKgC09qt/MbYijZWqn3XXhO1AXZW3NUVNfs0xDt7J5qfvZ1tGtNbRs3NzJ8cjHLM+FutIMZkYAhsVMhJtygRs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gLLQPnXx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gLLQPnXx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4437C116C6; Thu, 2 Apr 2026 22:12:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775167923; bh=yPWQ8Lu8w3RP+W5pBE5AC0381sEeBDUcYqrijLfEx9Y=; h=Date:From:To:cc:Subject:In-Reply-To:References:From; b=gLLQPnXxPgvtSs+507MGuXdxGhEg8qkQBnZTqDmO/coGkdkDgIXxSHrhRnxNk0n90 gJ4Fj9S3DuebBtyvUy28qcIEeLCKGg4TE19hFoNBMLWlOwm66Jd6c0QksoBuDBZBcE dWdFb4T7noGOSMX/3FSh4NDTMbwyD+De5/3D8KBuhu/C90CMEVc3uAfVgaklr+WxMA SZgQuB2MhHbnq5C6ar53sEsFQqQ1eTraSeOf6IMka3hiA7tYK1NGHPZ1Zx22HhQs1S XapBQOP0uZgKtZhYT4GzEkRPM9VNSGVXk+Gge340bh2pUREsV+uvMqLyDlvTWLCYUH jmOVFk1Nw8HnQ== Date: Thu, 2 Apr 2026 16:11:59 -0600 (MDT) From: Paul Walmsley To: Osama Abdelkader cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Thomas Gleixner , Vladimir Kondratiev , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] riscv: panic from init_IRQ if IRQ handler stacks cannot be allocated In-Reply-To: <20260326232335.60353-1-osama.abdelkader@gmail.com> Message-ID: References: <20260326232335.60353-1-osama.abdelkader@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Hi, On Fri, 27 Mar 2026, Osama Abdelkader wrote: > init_irq_stacks() and init_irq_scs() may fail when arch_alloc_vmap_stack > or scs_alloc return NULL. Return -ENOMEM from both and call panic() once > from init_IRQ(), covering per-CPU IRQ stacks and shadow IRQ stacks > consistently. > > Signed-off-by: Osama Abdelkader This patch appears to be written with AI assistance. If so, it should be noted in the description. Please see https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-assistants.rst > --- > arch/riscv/kernel/irq.c | 43 ++++++++++++++++++++++++++++++----------- > 1 file changed, 32 insertions(+), 11 deletions(-) > > diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c > index b6af20bc300f..43392276f7f8 100644 > --- a/arch/riscv/kernel/irq.c > +++ b/arch/riscv/kernel/irq.c > @@ -5,6 +5,7 @@ > * Copyright (C) 2018 Christoph Hellwig > */ > > +#include > #include > #include > #include > @@ -75,41 +76,53 @@ DECLARE_PER_CPU(ulong *, irq_shadow_call_stack_ptr); > DEFINE_PER_CPU(ulong *, irq_shadow_call_stack_ptr); > #endif > > -static void init_irq_scs(void) > +static int __init init_irq_scs(void) > { > int cpu; > + void *s; > > if (!scs_is_enabled()) > - return; > + return 0; > > - for_each_possible_cpu(cpu) > - per_cpu(irq_shadow_call_stack_ptr, cpu) = > - scs_alloc(cpu_to_node(cpu)); > + for_each_possible_cpu(cpu) { > + s = scs_alloc(cpu_to_node(cpu)); > + if (!s) > + return -ENOMEM; I don't see why this bothers to return an error value if the sole caller is just going to panic. Best to panic here. Then no one reviewing this patch needs to be concerned about memory leaks. > + per_cpu(irq_shadow_call_stack_ptr, cpu) = s; > + } > + > + return 0; > } > > DEFINE_PER_CPU(ulong *, irq_stack_ptr); > > #ifdef CONFIG_VMAP_STACK > -static void init_irq_stacks(void) > +static int __init init_irq_stacks(void) > { > int cpu; > ulong *p; > > for_each_possible_cpu(cpu) { > p = arch_alloc_vmap_stack(IRQ_STACK_SIZE, cpu_to_node(cpu)); > + if (!p) > + return -ENOMEM; Same comment as the above. > per_cpu(irq_stack_ptr, cpu) = p; > } > + > + return 0; > } > #else > /* irq stack only needs to be 16 byte aligned - not IRQ_STACK_SIZE aligned. */ > DEFINE_PER_CPU_ALIGNED(ulong [IRQ_STACK_SIZE/sizeof(ulong)], irq_stack); > > -static void init_irq_stacks(void) > +static int __init init_irq_stacks(void) > { > int cpu; > > for_each_possible_cpu(cpu) > per_cpu(irq_stack_ptr, cpu) = per_cpu(irq_stack, cpu); > + > + return 0; Why? > } > #endif /* CONFIG_VMAP_STACK */ > > @@ -129,8 +142,15 @@ void do_softirq_own_stack(void) > #endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */ > > #else > -static void init_irq_scs(void) {} > -static void init_irq_stacks(void) {} > +static int __init init_irq_scs(void) > +{ > + return 0; > +} > + > +static int __init init_irq_stacks(void) > +{ > + return 0; > +} > #endif /* CONFIG_IRQ_STACKS */ > > int arch_show_interrupts(struct seq_file *p, int prec) > @@ -141,8 +161,9 @@ int arch_show_interrupts(struct seq_file *p, int prec) > > void __init init_IRQ(void) > { > - init_irq_scs(); > - init_irq_stacks(); > + if (init_irq_stacks() || init_irq_scs()) > + panic("Failed to allocate IRQ stack resources\n"); Any reason why the initialization order is reversed? > + > irqchip_init(); > if (!handle_arch_irq) > panic("No interrupt controller found."); > -- > 2.43.0 - Paul