From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: <linux-kernel@vger.kernel.org>
Cc: <x86@kernel.org>, <tglx@linutronix.de>, <mingo@redhat.com>,
<bp@alien8.de>, <dave.hansen@linux.intel.com>,
<tony.luck@intel.com>, <ashok.raj@intel.com>,
Yan Hua Wu <yanhua1.wu@intel.com>
Subject: Re: [PATCH 1/1] arch/x86/microcode/intel: Remove unnecessary cache writeback and invalidation
Date: Tue, 10 Sep 2024 11:35:35 -0700 [thread overview]
Message-ID: <dc3c2ba3-73db-4609-bc34-3181c44d0dd0@intel.com> (raw)
In-Reply-To: <20240701212012.21499-2-chang.seok.bae@intel.com>
On 7/1/2024 2:20 PM, Chang S. Bae wrote:
>
> Additionally, the side effects of doing this have been overlooked. It
> extends the CPU rendezvous time for late loading. The cache flush takes
> about 1x to 3.5x more time than needed for updating the microcode.
To provide more context, the latency impact was found to be more adverse
when late loading was staged using the new loading feature [1]. Its
enabling patch set will be posted once the specification is updated,
likely after the upcoming merge window. I will include this fix (v2) as
part of the series.
Thanks,
Chang
[1]: https://cdrdv2.intel.com/v1/dl/getContent/782715
prev parent reply other threads:[~2024-09-10 18:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-01 21:20 [PATCH 0/1] x86/microcode: Revert cache flush on Intel microcode loading Chang S. Bae
2024-07-01 21:20 ` [PATCH 1/1] arch/x86/microcode/intel: Remove unnecessary cache writeback and invalidation Chang S. Bae
2024-07-01 22:56 ` Dave Hansen
2024-07-03 20:50 ` Ashok Raj
2024-07-03 20:55 ` Dave Hansen
2024-07-03 21:03 ` Ashok Raj
2024-07-03 21:11 ` Dave Hansen
2024-07-03 21:33 ` Ashok Raj
2024-07-04 0:05 ` Chang S. Bae
2024-07-02 23:24 ` Chang S. Bae
2024-09-10 18:35 ` Chang S. Bae [this message]
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